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module Ntile(clk,reset,input_ready,output_ready,ip_port[0],ip_port[1],ip_port[2],ip_port[3],ip_port[4],op_port[0],op_port[1],op_port[2],op_port[3],op_port[4],credit_in[0],credit_in[1],credit_in[2],credit_in[3],credit_in[4],credit_out[0],credit_out[1],credit_out[2],credit_out[3],credit_out[4]);
// parameter ID=6'b111111;
parameter num_nb=5;
parameter data_width=32;
parameter NUM_VCS=3;
parameter num_ic=5;
parameter num_oc=5;
parameter vc_counter=2;
parameter ADDR_SIZE=6;
input clk;
input reset;
input ID;
input [data_width-1:0] ip_port[num_nb-1:0];
output reg [data_width-1:0] op_port[num_nb-1:0];
input [NUM_VCS-1:0] credit_in[num_nb-1:0];
output reg [NUM_VCS-1:0] credit_out[num_nb-1:0];
input [num_nb-1:0] input_ready ;// this signal is added by me !
output reg [num_nb-1:0] output_ready ;// this signal is added by me !
//???size below
wire [data_width-1:0] flit_sig [num_ic-1:0][num_oc-1:0];/// signals to connect data outport of ICs to the data inport of the OCs
wire [data_width-1:0] flit_cs_ic; /// data line from ipcore to input channel
wire [data_width-1:0] flit_oc_cr; /// data line from output channel to ipcore
wire [num_oc-1:0] rdy[num_ic-1:0]; /// ready signals from ICs to OCs of neighboring tiles ???? size
wire [num_ic-1:0] vcReq; /// Request signal for virtual channel allocation from IC to VCA
wire [1:0] opReq[num_ic-1:0]; /// Output port requested from IC to VCA
wire [num_ic-1:0] vcReady;/// Ready signal from VCA to IC ?? size is wrong!
wire [vc_counter-1:0]nextvc[num_ic-1:0]; /// Virtual channel id allocated from VCA to IC
wire [NUM_VCS-1:0] creditIC_CS; /// credit line from core channel to VCA and ipcore
wire [num_ic-1:0] rtReq; /// Routing request signal from IC to Ctr
wire [ADDR_SIZE-1:0] desReq[num_ic-1:0];/// Destination address from IC to Ctr
wire [ADDR_SIZE-1:0] srcAddr[num_ic-1:0];/// Source address from IC to Ctr
wire [num_ic-1:0] rtReady;/// Ready signal from Ctr to IC
wire [2:0] nextRt[num_ic-1:0];/// Route (output port) signal from Ctr to IC
generate
genvar i;
for(i=0;i<num_nb;i=i+1)
begin :block_2
Inputchannel m0 (.clk(clk),.reset(reset),.inport(ip_port[i]),.input_ready(input_ready[i]),.outport_ip(flit_sig[i][4]),.outport_e(flit_sig[i][0]),.outport_s(flit_sig[i][1]),
.outport_w(flit_sig[i][2]),.outport_n(flit_sig[i][3]),.outReady(rdy[i]),.vcRequest(vcReq[i]),.vcReady(vcReady[i]),.opRequest(opReq[i]),
.nextVCID(nextvc[i]),.credit_out(credit_out[i]),.rtRequest(rtReq[i]),.rtReady(rtReady[i]),.destAddress(desReq[i]),.sourceAddress(srcAddr[i]),.nextRt(nextRt[i]));
outputChannel out1(.clk(clk),.reset(reset),.inport_ip(flit_sig[4][i]),.inport_e(flit_sig[0][i]),.inport_s(flit_sig[1][i]),.inport_w(flit_sig[2][i]),.inport_n(flit_sig[3][i]),.credit(credit_in[i]),.outport(op_port[i]),.(inReady[0])(rdy[0][i]),.(inReady[1])(rdy[1][i]),.(inReady[2])(rdy[2][i]),.(inReady[3])(rdy[3][i]),.(inReady[4])(rdy[4][i]),.outReady(output_ready[i]));
end
endgenerate
VCAllocator VCA(.clk(clk),.reset(reset),.vcRequest_ip(vcReq[4]),.vcRequest_e(vcReq[0]),.vcRequest_s(vcReq[1]),.vcRequest_w(vcReq[2]),.vcRequest_n(vcReq[3]),
.opRequest_ip(opReq[4]),.opRequest_e(opReq[0]),.opRequest_s(opReq[1]),.opRequest_w(opReq[2]),.opRequest_n(opReq[3]),.vcReady_ip(vcReady[4]),.vcReady_e(vcReady[0]),
.vcReady_s(vcReady[1]),.vcReady_w(vcReady[2]),.vcReady_n(vcReady[3]),.nextVCID_ip(nextRt[4]),.nextVCID_e(nextRt[0]),.nextVCID_s(nextRt[1]),.nextVCID_w(nextRt[2]),
/*
generate
for(j=0;j<=4;j=j+1)
begin :block_3
outputChannel out(.clk(clk),.reset(reset),.inport_ip(flit_sig[4][j]),.inport_e(flit_sig[0][j]),.inport_s(flit_sig[1][j]),.inport_w(flit_sig[2][j]),.inport_n(flit_sig[3][j]),.credit(credit_in[j]),.outport(op_port[j]),.(inReady[0])(rdy[0][j]),.(inReady[1])(rdy[1][j]),.(inReady[2])(rdy[2][j]),.(inReady[3])(rdy[3][j]),.(inReady[4])(rdy[4][j]),.outReady(output_ready[j]));
end
endgenerate
*/
Control con(.clk(clk),.reset(reset),.id(ID),.rtRequest_ip(rtReq[4]),.rtRequest_e(rtReq[0]),.rtRequest_s(rtReq[1]),.rtRequest_w(rtReq[2]),.rtRequest_n(rtReq[3]),.destAddress_ip(desReq[4]),.destAddress_e(desReq[0]),.destAddress_s(desReq[1]),.destAddress_w(desReq[2]),.destAddress_n(desReq[3]),
.sourceAddress_ip(srcAddr[4]),.sourceAddress_e(srcAddr[0]),.sourceAddress_s(srcAddr[1]),.sourceAddress_w(srcAddr[2]),.sourceAddress_n(srcAddr[3]),.rtReady(rtReady),.nextRt_ip(nextRt[4]),.nextRt_e(nextRt[0]),.nextRt_s(nextRt[1]),.nextRt_w(nextRt[2]),.nextRt_n(nextRt[3]));
endmodule
** Error: F:/Modesim/Ntile/Ntile.v(54): near "(": syntax error, unexpected '(', expecting "IDENTIFIER" or "TYPE_IDENTIFIER"
** Error: F:/Modesim/Ntile/Ntile.v(77): near "Control": syntax error, unexpected "IDENTIFIER", expecting ".*" or '.
大家帮帮忙：假如有这样的提示，一般都是什么样的问题出错了？ |
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发表于 2010-5-11 10:30:48
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