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代码如下:
module CLK_COMPARE (
clk_ref,
clk_detected,
reset,
detect_o
);
input reset;
input clk_ref;
input clk_detected;
output detect_o;
reg [7:0] clk_ref_count;
reg [10:0] clk_detected_count;
always @(posedge clk_ref or negedge reset)
begin
if(!reset)
clk_ref_count <= 8'b0;
else
clk_ref_count <= clk_ref_count + 1;
end
assign reset_wire = (clk_ref_count == 8'hff)?1'b0:1'b1;
assign reset_clk_detecter = reset_wire & reset;
always @(posedge clk_detected or negedge reset_clk_detecter)
begin
if(!reset_clk_detecter)
clk_detected_count <= 11'b0;
else
clk_detected_count <= clk_detected_count + 1;
end
assign detect_o = (clk_detected_count > clk_ref_count)?1'b1:1'b0;
endmodule
不知道这样搞行不行,综合出来会不会有问题, |
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