ENTITY Test_FPGA Is
port(
sys_clk : in std_logic;
addr : in std_logic_vector(4 downto 0);
data: inout std_logic_vector(15 downto 0);
cs: in std_logic;
wr: in std_logic;
Pin1 : out std_logic;
Pin2 : out std_logic
);
--Register Address
CONSTANT CTRL_WORD_ADDR : std_logic_vector(4 downto 0) := "00100";
End Test_FPGA;
Architecture bhv of Test_FPGA is
signal reg : std_logic_vector(15 downto 0);
begin
process(wr)
begin
if (cs='0') then
elsif wr'event and wr='1' then --posedge
if (addr=CTRL_WORD_ADDR) then
reg<=data;
end if;
end if;
end process;
process(rd)
begin
if (cs='0') then
elsif rd'event and rd='1' then --posedge
if (addr=CTRL_WORD_ADDR) then
data<=reg;
end if;
end if;
end process;
process(reg)
begin
Pin1<=reg(0);
Pin2<=reg(1);
end process;
End bhv;
data 为三态信号,如何定义它的三态状态?高手指教!
process(rd)
begin
if (cs='0') then
elsif rd'event and rd='1' then --posedge
if (addr=CTRL_WORD_ADDR) then
data<=reg;
end if;
else data <= 'Z'; --还请高手来回答吧
end if;
end process;