这是我的程序的错误部分,错误肯定是在这里。但是我一直都不知道怎么改,都好多天了也没有头绪,希望哪位大牛能给一些帮助。先谢谢了。
if(clk'event and clk='1') then -- 时钟触发
for i in 31 downto 0 loop
if(msum(31)='0') --判断最高位是不是零,是则左移一位,计数器加一。
then
conter<=conter+'1' ;
else
exit;
end if;
msum<=msum1;
end loop;
end if;
报错:
Error (10001): Verilog HDL or VHDL error at addN.vhd(25): can't infer register for msum[0] because it does not hold its value outside the clock edge
Error (10001): Verilog HDL or VHDL error at addN.vhd(25): can't infer register for msum[1] because it does not hold its value outside the clock edge
Error (10001): Verilog HDL or VHDL error at addN.vhd(25): can't infer register for msum[2] because it does not hold its value outside the clock edge
Error (10001): Verilog HDL or VHDL error at addN.vhd(25): can't infer register for msum[3] because it does not hold its value outside the clock edge
Error (10001): Verilog HDL or VHDL error at addN.vhd(25): can't infer register for msum[4] because it does not hold its value outside the clock edge