在线咨询 切换到宽版
eetop公众号 创芯大讲堂 创芯人才网

 找回密码
 注册

手机号码,快捷登录

手机号码,快捷登录

搜帖子
查看: 7492|回复: 22

Voltage-to-Current Converter

[复制链接]
发表于 2009-6-25 16:04:26 | 显示全部楼层 |阅读模式

马上注册,结交更多好友,享用更多功能,让你轻松玩转社区。

您需要 登录 才可以下载或查看,没有账号?注册

×
In the paper 'A Wideband CMOS Variable Gain Amplifier With an Exponential Gain Control',a Voltage-to-Current Converter is realized and the structure is shown  in  the following figure。
lkyd.jpg

In the figure,VC** denotes the voltage copier and current generation。here  i don't understand why VC** can copy voltage from node A to node B。

Could anybody explain it? thank you。

[ 本帖最后由 wwm101 于 2009-6-25 16:16 编辑 ]
发表于 2009-6-25 16:27:57 | 显示全部楼层
hi, wwm101

I suspect that the gate of the other NMOS of the differential pair should be connected to node "B". So the negative feedback loop will be established, and all things will make sense. Please think about it, thanx.
回复 支持 反对

使用道具 举报

 楼主| 发表于 2009-6-25 20:55:25 | 显示全部楼层


   
原帖由 wind2000sp3 于 2009-6-25 16:27 发表
hi, wwm101

I suspect that the gate of the other NMOS of the differential pair should be connected to node "B". So the negative feedback loop will be established, and all things will make sense. Ple ...



Thank you for your reply.
But how to explain the function of the NMOS whose gate is connected to node"A" and source is connected to  the gate of differential pair of the other NOMS at the right side?  thank you.
回复 支持 反对

使用道具 举报

发表于 2009-6-26 09:34:50 | 显示全部楼层
wwm101 & waveguides:
Sorry to Mr. Waveguides, you are not totally right.
This NMOS is a Slew-Rate-enhancement element. In the case of node A is suddenly higher than node B by Vthn, this NMOS will be turned on very soon. At this transient, the gates of the current mirrors are pulled down, and node B is increased as a consequence.
From this analysis, we can find out that the differential mode input voltage of the differential pair will never be larger than Vthn, which makes the Opamp works in linear region all the time. Also, from this point of view, the NMOS' channel length will be the minimum length allowed in a given process, and its width will be as large as 100um, smaller or bigger, depending on the slew rate requirement.
回复 支持 反对

使用道具 举报

 楼主| 发表于 2009-6-26 16:14:45 | 显示全部楼层
wind2000sp3 &waveguides:
Thank you very much for your reply.
Here and now ,i  can understand it.
回复 支持 反对

使用道具 举报

发表于 2009-6-26 16:32:53 | 显示全部楼层
wwm101,
Thank you too, for your interesting topics. There are so few topics discussing Linear Analog techniques in this forum, instead, almost all the members attach there reference in their topics. This job should be completed by a junior clerk, not an IC engineer.
回复 支持 反对

使用道具 举报

 楼主| 发表于 2009-6-27 19:18:14 | 显示全部楼层


   
原帖由 waveguides 于 2009-6-27 09:06 发表
I still think there are a few problems with this cir. Actually quite a few. I'm not sure this would be a working cir or not. hehe



It can work when i connect the gate of the other NOMS of differential pair  at the right side to the node 'B' .
The simulation result   was shown in  the following.
But the result also shows that the NMOS doesn't enhance slew-rate significantly.
ujvc.jpg
schematic
zdhn.jpg
tran simulation result
回复 支持 反对

使用道具 举报

 楼主| 发表于 2009-6-27 19:25:07 | 显示全部楼层


   
原帖由 waveguides 于 2009-6-27 09:13 发表
Actually if it was supposed to work as 2003 described, there are much easier solution than this.


thank you for your reply.
what kind of? Can you describe it to me ,please .thank you again.
回复 支持 反对

使用道具 举报

发表于 2009-6-28 01:34:53 | 显示全部楼层
不错不错
回复 支持 反对

使用道具 举报

发表于 2009-6-28 03:32:51 | 显示全部楼层
无条件支持!!谢谢分享!!97
回复 支持 反对

使用道具 举报

您需要登录后才可以回帖 登录 | 注册

本版积分规则

关闭

站长推荐 上一条 /1 下一条

X

手机版| 小黑屋| 关于我们| 联系我们| 隐私声明| EETOP 创芯网
( 京ICP备:10050787号 京公网安备:11010502037710 )

GMT+8, 2025-9-13 08:48 , Processed in 0.022108 second(s), 6 queries , Gzip On, Redis On.

eetop公众号 创芯大讲堂 创芯人才网
快速回复 返回顶部 返回列表