关于7系列MIG的管脚绑定综合报错

叽叽喳喳xyf

配置好MIG核后直接调用它example_top.ucf文件  修改了几个管脚位置之后进行 编译综合 ，但是之后他就报出下面的错误。BANK34全是SSTL18 但是就只有他报错 不知道为什么 ， 求大神帮忙



Place:897 - The following IOBs have been locked (LOC constraint) to the
   I/O bank 34.
   They require a voltage reference supply from the VREF pin(s) within the same
   I/O bank to be available.
   The following VREF pins are currently locked and can't be used to supply the
   necessary reference
   IO Standard: Name = SSTL18_II, VREF = 0.90, VCCO = 1.80, TERM = NONE, DIR =
   BIDIR, DRIVE_STR = NR
List of locked IOB's:
   
ddr2_dq<2>
   
ddr2_dq<1>
   
ddr2_dq<4>
   
ddr2_dq<3>
   
ddr2_dq<15>
   
ddr2_dq<0>
   
ddr2_dq<9>
   
ddr2_dq<6>
   
ddr2_dq<5>
   
ddr2_dq<8>
   
ddr2_dq<7>
   
ddr2_dq<10>
   
ddr2_dq<11>
   
ddr2_dq<12>
   
ddr2_dq<13>
   
ddr2_dq<14>
ERRORack:1654 - The timing-driven placement phase encountered an error.