250MHz 10bit ADC进展与求助

fuyibin

原帖由 hyy95 于 2009-3-3 10:32 发表

                               
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another question,why are u using 1024 points to do the DFT while 16, 32 points is enough to test your ckts' THD?

more points to do DFT analysis, more accuracy spectrum you will get
for example
if you do 1024 points DFT for 250MHz sample clk, the adjacent two frequency different is 250M/1024=244KHz
if you do 32 points DFT for 250MHz sample clk, the adjacent two frequency different is 250M/32=7.8MHz
the more points DFT, the higher resolution you'll get

hyy95

原帖由 ipmsn5 于 2009-3-3 10:36 发表

                               
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纯顶贴，请问lz用的 op amp是什么样的结构，我现在用folded-cascode作不了那么大的带宽（只有600Mhz的 GBW），而且功耗很大（6mA），90nm/1.0V

just folded cascode?
what is your swing requirement?

hyy95

原帖由 fuyibin 于 2009-3-3 11:04 发表

                               
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more points to do DFT analysis, more accuracy spectrum you will getfor exampleif you do 1024 points DFT for 250MHz sample clk, the adjacent two frequency different is 250M/1024=244KHz if you ...

yeah, 1024 points can have more resolution though,
but, if you can find problems by using 16 points, why bother 1024 points in the first place. You can save a lot of time using 16, 32 points.

BTW, your THD results is too good for a 10 bit ADC. are u using real switches or ideal switches? real CMFB or ideal CMFB?

fuyibin

原帖由 hyy95 于 2009-3-3 13:23 发表

                               
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yeah, 1024 points can have more resolution though,
but, if you can find problems by using 16 points, why bother 1024 points in the first place. You can save a lot of time using 16, 32 points.

BT ...

swithes and CMFB are real devices
only Vref and VCM are ideal
I can not find problems

eyetolisten

You can use your switch with an ideal opamp and see how much THD you can get.
btw, what architeture of opamp do u use and how much UGBW for your first stage opamp?

[ 本帖最后由 eyetolisten 于 2009-3-3 14:20 编辑 ]

fuyibin

原帖由 eyetolisten 于 2009-3-3 13:41 发表

                               
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You can use your switch with an ideal opamp and see how much THD you can get.
btw, what architeture of opamp do u use and how much UGBW for your first stage opamp?

gainboost opamp open loop gain is about 83dB,
S/H opamp UGBW is about 1.1GHz

magicdog

s/h 结构?

prof3

Here are some comments:

1. UGB=1.1Ghz is not enough for 250Mhz 10bit.  The THD degradation is most likely due to too low UGB
    For some margin, UGB=2Ghz  at least
2. Using coherence sampling always, 1024 bit is enough for FFT. However, pls check S/H first with your first stage MDAC loading. Plot FFT of S/H output see if your THD meets.
3. What kind of 65nm you are using, G or LP, there are a lot of diference. If you are design at VDDA=1.1V, pls check with VDDA=1.2V see if yor THD improve or not.
4. Can you plot the Vres of each stage? Also check THD at 0dBFS for the OPA you are using.
5. Finally, if you have the ouptut data or waveforms, I can check for you.

Hopefully this will help you.

fuyibin

原帖由 prof3 于 2009-3-4 02:50 发表

                               
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Here are some comments:

1. UGB=1.1Ghz is not enough for 250Mhz 10bit.  The THD degradation is most likely due to too low UGB
    For some margin, UGB=2Ghz  at least
2. Using coherence sampling al ...

Thank you for your advice
1. UGB=1.1Ghz is not enough for 250Mhz 10bit.  The THD degradation is most likely
     due to too low UGB0
Becase of the sample hold is capacitor flip structure, its feedback factor is nearly 1.
The UGB=1.1GHz seems enough for 250MHz 10bit

2. Using coherence sampling always, 1024 bit is enough for FFT. However, pls check S/H first with your first stage MDAC loading. Plot FFT of S/H output see if your THD meets
S/H with loading test is OK. when the whole ADC circuit is connected together, run the top level simulation. Do 1024 DFT for the S/H output  sample signal(the connect point of S/H and MDAC1). It can reach -95dB SFDR
3 If you are design at VDDA=1.1V, pls check with VDDA=1.2V see if yor THD improve or not
   65nm process VDD is 1.0V. I have already over stress power supply a little. If worry about output range is too large, a smaller signal can be forced in in stead of full scale signal.

4 Can you plot the Vres of each stage? Also check THD at 0dBFS for the OPA you are using
   Yes, I have saved the Vres of each stage. The vres settling looks OK.
   I don't know the meaning of "THD at 0dBFS for the OPA "

5. I can't cut  some picture on work station. But I print some picture on paper.

I really hope you give me some information
Thanks a lot

prof3

1. For 10bit, need about 7 tor. And Settling time=Ts/2=2ns, acutally only 1.8ns due to non-overlapped clock. For GBW=1.1Ghz, 7 tor about 7*1/(2*pi*GBW)=1.1ns<1.8ns, the rest 0.7ns can be use for slewing. If GBW=1.1Ghz is the worst case. It maybe fine for S&H.
However for MDAC, for 1.5bit/stage, it may be not. since now total 7/(2*pi*0.5*GBW)=2.2ns>1.8ns. It will harm your THD.

2. If your S/H is ok (-90dB below), why the whole simulation only -6xdB? Pls check Linearity of 1st MDAC using three point input signal to get corresponding three vres, then plot Vres vs Vin to see how linear it is. I believe, that will be the issue.

3. For 65nm 1V device can be stresss to 1.1V for sure. What I means is try to avoid large signal gain distortion for the OPA. This is why I ask you to try 1.2V. I am not going to ask you put your circuit work under 1.2V, only ask you to run simulation at 1.2V to see if the results get better

4. Another suggestion is pls pay attention when you check the FFT results. Using 1.111Mhz(cohenent to 250Mhz) input to check FFT see if better and calculate THD and compared with the standalone block. If ok, then increase input frequency and run again see where THD will degrade. If no change, then Gain is a suspicous issue and however, if degradation a lot, then BW is the factor instead.

Hopefully it helps you.