250MHz 10bit ADC进展与求助

fuyibin

原帖由 vdslafe 于 2009-3-4 17:17 发表

                               
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我想弄清楚，ADC sim 你看到的是62dB THD 还是62dB SFDR.  
如果是62dB THD, 那说明你是perfect, 62dB SFDR 说明还要debug.

在这种设置下，INL 能看到的single tone test 都能看见，后者还快的多。

clk 砍 ...

哦，不好意思，我误导大家了
是HD3=-62.4dB HD5=-68.8dB  THD=-58.5dB
我看到的SFDR就是 HD3 最高，接着是HD5

fuyibin

原帖由 vdslafe 于 2009-3-4 17:17 发表

                               
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我想弄清楚，ADC sim 你看到的是62dB THD 还是62dB SFDR.  
如果是62dB THD, 那说明你是perfect, 62dB SFDR 说明还要debug.

在这种设置下，INL 能看到的single tone test 都能看见，后者还快的多。

clk 砍 ...

clk 砍一半，linearity 提高2dB, 说明settling 是limiting factor
是什么意思？我觉得clk 再慢，THD 也不会好到哪里去啊，说明250MHz的已经基本settle了吧

还有一点，如果THD=-62dB，而不是62dB SFDR ， 那也不能说明是perfect啊 ，
一般人家的THD不是要远远好于6.02*N+1.76dB 么？
看他们的实测结果都是远好于的，14bitADC 的THD=-95dB了

hardmany

跑tran时，精度要够，不知你的max step是多少？至少要少于采样周期，这样做DFT才够准确。你的THD是怎么得来的？把数据保存下来，用Matlab分析的吗？

fuyibin

原帖由 hardmany 于 2009-3-4 18:02 发表

                               
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跑tran时，精度要够，不知你的max step是多少？至少要少于采样周期，这样做DFT才够准确。你的THD是怎么得来的？把数据保存下来，用Matlab分析的吗？

在spectre里面跑的啊，步长很小的，仿真精度设的比较高的，精度再高对结果影响不大的
我THD是在spectre的计算器里面直接算的啊
计算器里面直接有函数可以算THD和做DFT 分析的

hardmany

至于仿真精度问题，你可以看一下cadence帮助文件，关于DFT分析的，里面有说明。我没用过calculator做THD，我一般是把数据保存下来用matlab分析。其中保存下来的数据中第一个数据很大，也就是直流项，很影响SNR的结果，不知道用calculator做会有这个现象没？

prof3

1. 10bit ADC of course can have THD much better -60dB. However, it can NOT have SNR > 60dB.
From your simulation, THD=-62dB acutally a little bit lower. If your clock is ideal, reference is ideal, time-step is accurate enough, then the rest three factors will be settling and FFT analysis and Raw data
2. For your result, you said your settling is ok. Can I ask how accurate the settling by the end of amplify-cycle, is 0.1%, 0.01% or in between? If that the case, that will be the reason why your THD around -62dB.
3. For FFT analysis, you said you use cohenent sampling, rectangle window, 2^N point, integer cycle, all look fine. So your FFT method is ok.
4. For RAW data, I never use Cadence ideal DAC model. Usually I get the data from Spice simulation result and send it to Matlab. Basically Matlab will convert 010011... into an ideal decimal value and FFT, this is no any quantization error. If you did like this, RAW data processing also looks ok.
5. For MDAC, your GBW=1.8Ghz looks normal. Not that much margin. Actually, if your MDAC can get GBW=1.8Ghz, you can even push SAH higher than 1.1Ghz, then your hgih frequency performnace looks great.

6. Based on above, I am still doubling the settling, can you  show some pic. see how well the settling behavoir? Is completely settling or not? sometimes "false" settling especially your OPA looks complicated.

Hopefully it helps.

fuyibin

又发现一些潜在因素，导致每级的THD很好，而合起来的THD变差
在刚开始gain boost opamp的simulation时候，看到的opamp 的open loop Gain = 83dB
以为gain够了，就没有太多的关注了
昨天有同事提醒查一下每个stage的gain是否等于2，误差是多少
今天早上又跑了瞬态，看看settle后的误差到底是多少

	Input mV	Output mV	Error mV	Gain supposed dB	AC Gain dB	Stage gain
S/H	500	499.9	0.1	74	82	0.9998
MDAC1	250	499.83	0.17	75.4	83	1.99932
MDAC2	250	499.85	0.15	76.5	83	1.9994
MDAC3	250	499.77	0.23	72.8	83	1.9991
MDAC7	250	480.6	19.4	34.2	40	1.9224

在测AC gain的时候，opamp的输出基本在共模附近，但是到输出最大/最小幅度时候，opamp的gain已经没有原来这么大了，主要原因应该是cascode transistor的vds减小，越来越趋近于vdsat，导致输出阻抗减小，使得opamp的gain下降
但是我不能判断现在这个每一级的gain error 能导致整个ADC多大的THD

prof3

Hey man,

I told you before to check OPA Gain at 0dBFS input and you said your OPA gain is ok. 0dBFS means your OPA at maximal swing and at this time the gain will be the worst case.  Look at your table, the first three stage is OK. but the MDAC7 looks not enough. For simplicity, you can use your first 3 stage OPA to replace MDAC7's OPA to see if better. Of course, you have to fix Vdsat problem finally.

prof3

When you doing SCF or SC-Based type ADC etc, OPA gain must be simulated under large signal level. AC gain is completely not enough because your OPA does NOT always work at 共模附近.

Remember again, 在测AC gain的时候，opamp的输出must be是输出最大/最小幅度时候(plot a Gain vs Vout is better)

fuyibin

原帖由 prof3 于 2009-3-5 09:55 发表

                               
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Hey man,

I told you before to check OPA Gain at 0dBFS input and you said your OPA gain is ok. 0dBFS means your OPA at maximal swing and at this time the gain will be the worst case.  Look at your t ...

I have tried to replace MDAC7 with MDAC3.
And the result of distortion HD3=-62dB THD=-59dB was got when the MDAC3 was used in stage7 and stage8!
However, I have also tried MDAC7 uesd in stage7 and stage8. The result is almost identical.
So I think the low gain in stage7 and stage8 is not a critical factor in ADC top level THD degradation.