2.4-3.2Gbps clock and data recovery circuit

kevinwjs

1. INTRODUCTION................................................................................................ 1
1.1. Motivation........................................................................................................1
1.2. Thesis Organization .........................................................................................2
2. CLOCK AND DATA RECOVERY STRUCTURES IN SERIAL
COMMUNICATION SYSTEMS.................................................................................. 4
2.1. Introduction......................................................................................................4
2.2. Clock and Data Recovery in Serial Data Transmission...................................5
2.3. Methods of Clock and Data Recovery.............................................................7
2.3.1. Disk Drive Clock Recovery..........................................................................9
2.3.2. Generating High-Speed Digital Clocks On-Chip .........................................9
2.3.3. Over-sampled Data Conversion....................................................................9
2.3.4. Wireless Communication..............................................................................9
2.4. Basic Clock and Data Recovery Architectures .............................................. 10
2.4.1. Properties of Non-Return to Zero (NRZ) Data........................................... 10
2.4.2. Clock Recovery Architectures .................................................................... 13
3. PERFORMANCE MEASURES OF PLL BASED CLOCK AND DATA
RECOVERY CIRCUITS............................................................................................. 20
3.1. Introduction.................................................................................................... 20
3.2. Phase-Locked Loop Fundamentals ................................................................ 20
3.3. Loop Bandwidth and Damping Factor........................................................... 24
3.4. Lock Time (Settling Time)............................................................................. 25
3.5. Lock Range (Tracking Range) ....................................................................... 27
3.6. Acquisition of Lock........................................................................................ 29
3.6.1. Acquisition Time ........................................................................................ 31
3.6.2. Aided Acquisition....................................................................................... 32
3.7. Timing Jitter Definitions................................................................................ 33
3.7.1. Deterministic Jitter...................................................................................... 34
3.7.2. Random Jitter.............................................................................................. 35
3.8. SONET Jitter Specifications .......................................................................... 37
3.8.1. SONET Jitter Tolerance.............................................................................. 38
3.8.2. SONET Jitter Transfer ................................................................................ 40
3.8.3. SONET Jitter Generation............................................................................ 43
4. MODELING AND SIMULATING PLL BASED CLOCK RECOVERY
CIRCUIT IN MATLAB............................................................................................... 44
4.1. Introduction.................................................................................................... 44
4.2. Two-Loop Architecture.................................................................................. 45
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4.3. Determining Loop Dynamics......................................................................... 46
4.4. Simulink Modelling of Two-Loop Clock and Data Recovery....................... 55
4.4.1. Coarse Loop Modelling .............................................................................. 55
4.4.2. Fine Loop Modelling .................................................................................. 58
4.4.3. Two-Loop Clock and Data Recovery Modelling ....................................... 60
5. ARCHITECTURE COMPONENTS: GENERAL TECHNOLOGY
REVIEW & COARSE LOOP ..................................................................................... 64
5.1. Introduction.................................................................................................... 64
5.2. General Considerations .................................................................................. 65
5.2.1. Substrate Current Injection......................................................................... 65
5.2.2. Common-mode Noise Immunity................................................................ 66
5.2.3. Differential vs. Single-Ended Signalling.................................................... 66
5.2.4. Technology and Transistors........................................................................ 67
5.2.5. Case Definitions.......................................................................................... 73
5.3. Design of Coarse Loop Components: ............................................................ 73
5.3.1. Design of Phase-Frequency Detector ......................................................... 73
5.3.2. Design of Differential Charge Pump .......................................................... 80
5.3.3. Design of Common-Mode Feedback (CMFB) Circuit ............................... 90
5.3.4. Design of Divide-by-16 Circuit .................................................................. 92
5.3.5. Design of Lock Detector............................................................................. 94
6. ARCHITECTURE COMPONENTS: FINE LOOP & DIFFERENTIAL
VCO.............................................................................................................................100
6.1. Introduction.................................................................................................. 100
6.2. Design of Fine Loop Components ............................................................... 100
6.2.1. Design of Differential Phase Detector ...................................................... 100
6.2.1.1. Design of Differential Master-Slave Flip-Flop.................................. 105
6.2.1.2. Design of Delay Cell.......................................................................... 110
6.2.1.3. Design of Differential XOR............................................................... 111
6.2.2. Design of Differential Charge Pump ........................................................ 113
6.2.3. Design of Differential Loop Filter ............................................................ 119
6.3. Design of Differential Voltage Controlled Oscillator (VCO)...................... 121
6.3.1. Ring Oscillator VCO................................................................................ 123
6.3.2. Construction of the Differential Ring Oscillator ...................................... 129
6.3.3. Design of Differential Delay Stage and Self-Biasing Circuit................... 132
6.3.4. Design of VCO Output Buffer.................................................................. 138
7. TOP LEVEL CONSTRUCTION of THE CIRCUIT AND LAYOUT
CONSIDERATIONS.................................................................................................. 141
7.1. Introduction.................................................................................................. 141
7.2. Top-Level Construction of the Circuit......................................................... 141
7.3. Top-Level Simulations of the Circuit .......................................................... 144
7.4. System Level Functionality of Clock and Data Recovery Circuit............... 149
7.5. Layout Considerations ................................................................................. 152
7.5.1. Layer Sharing............................................................................................ 152
7.5.2. Reliability.................................................................................................. 153
7.5.3. Symmetry and Placing.............................................................................. 153
7.5.4. Bending on Data Paths.............................................................................. 155
7.5.5. Shielding................................................................................................... 155
7.5.6. Dummy Components ................................................................................ 156
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7.6. The Layout ................................................................................................... 157
8. CONCLUSION................................................................................................. 163

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