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1. A Robust Energy/Area-Efficient Forwarded-Clock Receiver With All-Digital Clock and Data Recovery in 28-nm CMOS for High-Density Interconnects -- Chen, S.
2. A 1.6Gbps Digital Clock and Data Recovery Circuit --- Hanumolu, P.K. ;
3. Digital clock and data recovery circuit design: Challenges and tradeoffs -- Talegaonkar, M. ; |
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