怎样使用GSR全局信号作为我的module的reset信号？

yinchb

xilinx的文件中举了这样一个例子，可以使用STARTUP模块或不使用STARTUP模块，这个例子是不使用STARTUP模块。可是那个GSR信号要怎么描述呢，就这样系统能识别吗？还有，FDCE，STARTUP模块根本就没有出现，编译也没有通过，应该怎样调用呢？
module my_counter (CLK, D, Q, COUT);
input CLK, D;
output Q;
output [3:0] COUT;
wire GSR;
reg [3:0] COUT;
always @(posedge GSR or posedge CLK)
begin
if (GSR == 1’b1)
COUT = 4’h0;
else
COUT = COUT + 1’b1;
end
// GSR is modeled as a wire within a global module.
// So, CLR does not need to be connected to GSR and
// the flop will still be reset with GSR.
FDCE U0 (.Q (Q), .D (D), .C (CLK), .CE (1'b1), .CLR
(1’b0));
endmodule
下面的例子是使用STARTUP模块：
module my_counter (MYGSR, CLK, D, Q, COUT);
input MYGSR, CLK, D;
output Q;
output [3:0] COUT;
reg [3:0] COUT;
always @(posedge MYGSR or posedge CLK)
begin
if (MYGSR == 1’b1)
COUT = 4’h0;
else
COUT = COUT + 1’b1;
end
// GSR is modeled as a wire within a global
// module.So, CLR does not need to be connected
// to GSR and the flop will still be reset with GSR.
FDCE U0 (.Q (Q), .D (D), .C (CLK), .CE (1’b1),
.CLR (1’b0));
STARTUP U1 (.GSR (MYGSR), .GTS (1’b0), .CLK
(1’b0));
endmodule
可是，FDCE，

一声叹息

GSR能不能被综合工具自动识别可能与所选器件有关，见Xilinx的说明。
The use of Global Set/Reset Resource (GSR) in Virtex, Virtex-E, Virtex-II and Spartan-II devices must be considered carefully. Synthesis tools do not automatically infer GSRs for these devices; however, STARTUP_VIRTEX, STARTUP_VIRTEX2 and STARTUP_SPARTAN2 can be instantiated in your HDL code to access the GSR resources. Xilinx® recommends that for Virtex, Virtex-E, and Spartan-II designs, you write the high fanout set/reset signal explicitly in the HDL code, and not use the STARTUP_VIRTEX, STARTUP_VIRTEX2 or STARTUP_SPARTAN2 blocks. There are two advantages to this method.
This method gives you a faster speed. The set/reset signals are routed onto the secondary longlines in the device, which are global lines with minimal skews and high speed. Therefore, the reset/set signals on the secondary lines are much faster than the GSR nets of the STARTUP_VIRTEX block. Since Virtex is rich in routings, placing and routing this signal on the global lines can be easily done by our software.
The trce program analyzes the delays of the explicitly written set/reset signals. You can read the TWR file (report file of the trce program) and find out exactly how fast your design’s speed is. The trce program does not analyze the delays on the GSR net of the STARTUP_VIRTEX, STARTUP_VIRTEX2, or STARTUP_SPARTAN2. Hence, using an explicit set/reset signal improves your design accountability.
For Virtex/E/II/II Pro/II Pro X and Spartan-II/3 devices, the Global Set/Reset (GSR) signal is, by default, set to active high (globally resets device when logic equals 1). You can change this to active low by inverting the GSR signal before connecting it to the GSR input of the STARTUP component

yinchb

可是model的port list中，有D，Q，那么岂不是要为其分配fpga上的端口，而这些端口怎么分配呢？

一声叹息

不是连到了FDCE的D和Q了吗？

yinchb

系统会自动识别这个D，Q不要求你去连到外部引脚？
还是会要你连到PDCE？还有，PDCE是什么？在哪里？

yinchb

出现error了？
ERROR:NgdBuild:424 - The STARTUP symbol "U1" is not supported in the spartan2
   architecture. None of the currently installed architectures support STARTUP
   symbols.
ERROR: NGDBUILD failed
Reason:
不是说可以支持spartan2吗？还有NGDBLUILD fail是为什么呢？

bravelu

你到底要做什么？实现什么功能？

yinchb

想用它来作为我的moduel的全局复位信号。当系统加电后为低，此时对寄存器赋值，然后变高，执行我的逻辑。

bravelu

就是上电复位吧，你不用加这个模块，本身也会有这个功能的。

一声叹息

看一下我贴的Xilinx的说明。如果你使用SpartanII，Xilinx比不建议你这样用，如果你非要用，不要实例化STARTUP，而要实例化STARTUP_SPARTAN2。