|
马上注册,结交更多好友,享用更多功能,让你轻松玩转社区。
您需要 登录 才可以下载或查看,没有账号?注册
x
工作地点:武汉
Requirement:
- Working from SerDes standards to block specifications, you quickly identify potential circuit architectures and successful design strategies.
- You must have experience in designing at least two of the following key functions: Clock and Data Recovery, PLLs, Transmitters, Receivers, Bandgaps.
- You will work with a cross functional design team of analog and digital designers from a wide variety of backgrounds.
- Our environment is best in class with a full suite of IC design tools supplemented by custom, in-house tools supported by an experienced software/CAD team.
- Experience with tools for schematic entry, IC layout and SPICE simulation is required.
- Knowledgeable in Verilog-A for analog behavioral modeling and simulation-control/data-capture.
- Experience with TCL, perl, C, python, MATLAB, or other scripting languages is desired.
感兴趣的童鞋请发简历至qq邮箱: 54066483@qq.com |
|