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工作地点：武汉
Requirement:
- Working from SerDes standards to block specifications, you quickly identify potential circuit architectures and successful design strategies.
- You must have experience in designing at least two of the following key functions: Clock and Data Recovery, PLLs, Transmitters, Receivers, Bandgaps.
- You will work with a cross functional design team of analog and digital designers from a wide variety of backgrounds.
- Our environment is best in class with a full suite of IC design tools supplemented by custom, in-house tools supported by an experienced software/CAD team.
- Experience with tools for schematic entry, IC layout and SPICE simulation is required.
- Knowledgeable in Verilog-A for analog behavioral modeling and simulation-control/data-capture.
- Experience with TCL, perl, C, python, MATLAB, or other scripting languages is desired.
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eetop公众号
创芯大讲堂
创芯人才网
发表于 2014-9-4 16:51:17
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