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发表于 2013-8-16 16:52:55
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回复 5# wgang0224
VCO 最高可以到1300MHz。给PLL输100MHz, multiplier设5, divider设1, 就可以生成500MHz的
Clock Networks and PLLs in Cyclone IV Devices, 5-26:
Each Cyclone IV PLL provides clock synthesis for PLL output ports using
M/(N*post-scale counter) scaling factors. The input clock is divided by a pre-scale
factor, N, and is then multiplied by the M feedback factor. The control loop drives the
VCO to match fIN (M/N). Each output port has a unique post-scale counter that
divides down the high-frequency VCO. For multiple PLL outputs with different
frequencies, the VCO value is the least common multiple of the output frequencies
that meets its frequency specifications. For example, if output frequencies required
from one PLL are 33 and 66 MHz, the Quartus II software sets the VCO to 660 MHz
(the least common multiple of 33 and 66 MHz in the VCO range). Then, the post-scale
counters scale down the VCO frequency for each output port.
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