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包括两个文件。
目录如下:
其一:
CONTENTS
1. INTRODUCTION
2. ANALOG IC DESIGN FLOW AND REQUIRED TOOLS
3. SETTING YOUR UNIX ENVIRONMENT
4. RUNNING CADENCE
5. ANALOG DESIGN WITH CADENCE DESIGN FRAMEWORK II
5.1. Library Creation and Selection of Technology
5.2. Schematic Entry with Composer
5.2.1. Symbol Creation
5.3. Simulation
5.3.1. Setting simulator
5.3.2. Setting models
5.3.3. Setting design variables
5.3.4. Selecting the analysis
5.3.5. Running the simulation
5.3.6. Plotting the simulation results
5.4. Layout
5.4.1. Basic Full-Custom Layout
5.4.2. Full custom layout using pcells
5.4.3. Fill-custom layout using Virtuoso XL
5.4.4. Hierarchical layout
5.5. Verification
5.5.1. Design Rule Check (DRC)
5.5.2. Layout versus Schematic (LVS)
6. TRANSFER TO FOUNDRY
7. PRINTING IN CADENCE
8. REFERENCES
APPENDIX: ADVANCED TOPICS
A.1. TRANSITION GUIDE FROM TANNER TOOLS TO CADENCE
A.2. INTRODUCTION TO SKILL
A.3. LOGIC SIMULATION WITH VERILOG
其二:
Contents
1 Introduction
2 Virtuoso Layout Editing
2.1 Setting Up the Environment
2.2 Layer Selection Window (LSW)
2.3 Creating Shapes and Objects
2.4 Selecting Objects for Edit
2.4.1 Selection modes
2.4.2 Selecting objects
2.5 Editing Objects
2.5.1 Moving Objects
2.5.2 Copying Objects
2.5.3 Deleting Objects
2.5.4 Stretching Objects
2.5.5 Merging Objects
2.6 Saving the Design
3 Inverter Layout : Design rule & Mask layers
3.1 Design Rules
3.2 Mask Layers
3.2.1 Diffusion areas for source, drain, and substrate contacts
3.2.2 N-well regions
3.2.3 Contacts
3.2.4 Metal power ground and signal routing layers
4 Layout Verification
4.1 Design Rule Check (DRC)
4.2 Connectivity Extraction
4.3 Layout Versus Schematic (LVS) Software
4.3.1 Running LVS
4.3.2 Displaying the Errors
4.3.3 Probing the Schematic and Layout
5 Layout Simulation
6 Hierarchal Layout Editing |
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