xAccel Joker 设计平台

oxygen_chu

xAccel Joker's [Code Check] for Verilog/SystemVerilog is a realtime code checker that serves as an essential tool for hardware designers, providing immediate feedback, improving productivity, and ensuring high-quality designs. By catching errors early and promoting good coding practices, it significantly reduces the risk of costly design flaws and accelerates the development process.

oxygen_chu

yeewang 发表于 2024-9-7 17:05
interesting.  you can call it an EDA but a real one with value to users need more functionalities  ...

2024.09.11 Update

xAccel Joker's [Code Decrypt]

yeewang

oxygen_chu 发表于 2024-9-11 21:42
2024.09.11 Update

xAccel Joker's [Code Decrypt]

code decrypt?  what is this?  decrypting IEEE1735 encryption?

oxygen_chu

yeewang 发表于 2024-9-12 09:23
code decrypt?  what is this?  decrypting IEEE1735 encryption?

not only 1735.
just check the BaiduPan video I have uploaded.

skahill

Interesting, thanks for sharing...

yeewang

oxygen_chu 发表于 2024-9-12 11:27
not only 1735.
just check the BaiduPan video I have uploaded.

saw it.  my 2 cents: if you plan to publish your sw some day, this decrypting function (it is illegal to do this publicly) will be a problem.  if you don't care about that, you also need to add "batch decrypt".   it's often a bunch of files encrypted.  people would want to decrypt all at once.
keep up the good job.

dont forget to add an api for LLM, coding assistance is now very mucb desired.

oxygen_chu

yeewang 发表于 2024-9-12 12:58
saw it.  my 2 cents: if you plan to publish your sw some day, this decrypting function (it is ille ...

1. Decryption will be publicly removed.

2. LLM and Code-Template is integrated, and you will see later.

oxygen_chu

yeewang 发表于 2024-9-12 12:58
saw it.  my 2 cents: if you plan to publish your sw some day, this decrypting function (it is ille ...

2024.09.12 Update in BaiduPan
xAccel Joker's [Code Template] boost productivity and reduce coding errors, featuring high-performance and flexibility that let you instantly insert well-designed Verilog/SystemVerilog code and design (timing and physical) constraint. This streamlining design process with pre-validated code and constraints empowers engineers to write error-free, optimized code in seconds.

oxygen_chu

2024.09.12 Update in BaiduPan
xAccel Joker's [Code Template] boost productivity and reduce coding errors, featuring high-performance and flexibility that let you instantly insert well-designed Verilog/SystemVerilog code and design (timing and physical) constraint. This streamlining design process with pre-validated code and constraints empowers engineers to write error-free, optimized code in seconds.

oxygen_chu

yeewang 发表于 2024-9-7 17:05
interesting.  you can call it an EDA but a real one with value to users need more functionalities  ...

2024-09-19 BaiduPan Updated

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xAccel Joker [Simulation Coverage]