ESD Protection Design for Mixed-Voltage I/O(Ker)

semico_ljj · 发表于 2008-1-18 22:20:09

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ESD Protection Design by Using Only 1×VDD
Low-Voltage Devices for Mixed-Voltage I/O
Buffers with 3×VDD Input Tolerance

Ming-Dou Ker and Chang-Tzu Wang
Institute of Electronics, National Chiao-Tung University
1001 Ta Hsueh Road, Hsinchu, Taiwan, E-mail: mdker@ieee.org

Abstract
A new electrostatic discharge (ESD) protection design
by using only 1×VDD low-voltage devices for mixed-voltage I/O
buffer with 3×VDD input tolerance is proposed. A special ESD
detection circuit has been proposed to improve ESD protection
efficiency of ESD clamp device by substrate-triggered technique
to achieve high ESD level. This design has been successfully
verified in a 0.13-μm CMOS process to provide an excellent
circuit solution for on-chip ESD protection in the mixed-voltage
I/O buffers with 3×VDD input tolerance.

semico_ljj · 发表于 2008-1-18 22:21:45

CONCLUSION
A novel circuit solution on ESD protection design realized
with 1×VDD devices for mixed-voltage I/O buffer with
3×VDD input tolerance and single VDD supply has been
successfully verified in a 0.13-μm CMOS process. The
four-mode (PS, NS, PD, and ND) ESD stresses and pin-to-pin
ESD stresses on the 1.2/3.3-V mixed-voltage I/O buffer can be
effectively discharged by the proposed ESD protection scheme
without gate-oxide reliability issue. The turn-on behavior of the
ESD clamp device has been measured to verify the
effectiveness of the ESD detection circuit. The experimental
results have confirmed that the ESD robustness of the 3×VDD
mixed-voltage I/O buffer can be significantly increased up to
8kV with the proposed ESD protection scheme.

semico_ljj · 发表于 2008-1-18 22:22:48

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