CMOS Power Amplifier with ESD Protection (Ker)

semico_ljj

CMOS Power Amplifier with ESD Protection Design
Merged in Matching Network


Yu-Da Shiu1, Bo-Shih Huang1, and Ming-Dou Ker2

1SoC Technology Center, Industrial Technology Research Institute, Hsinchu, Taiwan.
2Nanoelectronics and Gigascale Systems Laboratory, Institute of Electronics, National Chiao-Tung University, Hsinchu, Taiwan.
Email: {ydshiu, [email=huangboshi}@itri.org.tw]huangboshi}@itri.org.tw[/email] and mdker@ieee.org

Abstract

A power amplifier (PA) with combination of ESD
protection circuit and matching network into single block was
proposed and implemented in a 0.18-μm CMOS process. By
comprising ESD protection function into the matching network,
this design omits individual I/O ESD clamps to alleviate
loading that degrades RF performances. According to the
experimental results, the ESD protection circuit with LC
configuration contributes a 3.0-kV human body model (HBM)
ESD robustness without significant degradation on RF
performances of the PA for 2.4-GHz RF applications.

semico_ljj

CONCLUSIONS
A PA with ESD protection circuit in a 0.18-μm CMOS
process has been designed, fabricated, and successfully
verified. The combination of matching networks with ESD
protection solution benefits not only RF performance but
also ESD robustness. From the experimental results, the
proposed ESD protection design on the PA provides high
HBM ESD robustness of over 3.0 kV without significant
degradation on RF performance. The ESD protection design
merged into the matching network is a simple and effective
solution of ESD protection for RF PA.

semico_ljj

REFERENCES
[1] M.-D. Ker, W.-Y. Lo, C.-M. Lee, C.-P. Chen, and H.-S.
Kao, “ESD protection design for 900-MHz RF receiver
with 8-kV HBM ESD robustness,” in Dig. of IEEE
RFIC Symp., 2002, pp. 427-430.
[2] G. Chen, H. Feng, H. Xie, R. Zhan, Q. Wu, X. Guan, A.
Wang, K. Takasuka, S. Tamura, Z. Wang, and C.
Zhang, “RF characterization of. ESD protection
structures,” in Dig. of IEEE RFIC Symp., 2004, pp.
379-382.
[3] V. Vassilev, S. Thijs, P. Lajo Segura, G. Groeneseken,
P. Wambacq, P. Leroux, M. Steyaert, M. Natarajan, and
H. Maes, “Co-design methodology to provide high ESD
protection levels in the advanced RF circuits,” in Proc.
of EOS/ESD Symp., 2003, pp. 195-203.
[4] M.-D. Ker, Y.-W. Hsiao, and B.-J. Kuo “ESD
protection design for 1- to 10-GHz distributed amplifier
in CMOS technology,” IEEE Trans. on Microwave
Theory and Techniques, vol. 53, no. 9, pp. 2672-2681,
Sept. 2005.
[5] S. Hyvonen and E. Rosenbaum, “Diode-based tuned
ESD protection for 5.25-GHz CMOS LNAs,” in Proc.
of EOS/ESD Symp., 2005, pp. 9-17.
[6] M.-D. Ker, “Whole-chip ESD protection design with
efficient VDD-to-VSS ESD clamp circuit for
submicron CMOS VLSI,” IEEE Trans. on Electron
Devices, vol. 46, no.1 , pp. 173-183, Jan. 1999.
[7] Electrostatic discharge (ESD) sensitivity testing –
human body model (HBM), International Standard,
JEDEC EIA / JESD22- A144-B, 2000.

flyfeng

十分感谢

denap

THanks for sharing!!

raisin80

merci tous

alex_bai

culight

xiexie

pper1983

好东西

muyangtong