In 1994, he joined the VLSI Design Department of the Computer and Communication Research Laboratories (CCL), Industrial Technology Research Institute (ITRI), Taiwan, as a Circuit Design Engineer. In 1998, he was the Department Manager in the VLSI Design Division of CCL/ITRI. Now, he has been a Full Professor in the Department of Electronics Engineering, National Chiao-Tung University. In the field of reliability and quality design for CMOS integrated circuits, he has published over 270 technical papers in international journals and conferences.
He has proposed many inventions to improve reliability and quality of integrated circuits, which have granted with 113 U.S. patents and 123 ROC (Taiwan) patents. His current research topics include reliabiliy and quality design for nanoelectronics and gigascale systems, high-speed and mixed-voltage I/O interface circuits, and on-glass circuits for system-on-panel applications in TFT LCD display. Dr. Ker had been invited to teach or to consult reliability and quality design for integrated circuits by hundreds of design houses and semiconductor companies in the Science-Based Industrial Park, Hsinchu, Taiwan; in the Silicon Valley, San Jose, California, USA; in Singapore; and in the Mainland China.
Dr. Ker has served as member of the Technical Program Committee and Session Chair of numerous international conferences He was selected as the Distinguished Lecturer in IEEE CAS Society for 2006-2007. Now, he also served as Associate Editor of IEEE Trans. on VLSI Systems. He was the Foundation President of Taiwan ESD Association since 2001. Dr. Ker has received many research awards from ITRI, National Science Council, National Chiao-Tung University, and the Dragon Thesis Award from Acer Foundation. In 2003, he was selected as one of the Ten Outstanding Young Persons in Taiwan by Junior Chamber International (JCI). In 2005, one of his patents on ESD protection design has been awarded with the National Invention Award in Taiwan.
其最有名的一部专著：
互補式金氧半積體電路之靜電放電防護ESD (Electrostatic Discharge) Protection in CMOS Integrated Circuits
Overview on ESD protection design for mixed-voltage I/O interfaces with high-voltage-tolerant power-rail ESD clamp circuits in low-voltage thin-oxide CMOS technology
Ming-Dou Ker and W.-J. Chang “Overview on ESD protection design for mixed-voltage I/O interfaces with high-voltage-tolerant power-rail ESD clamp circuits in low-voltage thin-oxide CMOS technology,”Microelectronics Reliability, vol. 47, no. 1, pp. 27-35, Jan. 2007.
Abstract
Electrostatic discharge (ESD) protection design for mixed-voltage I/O interfaces has been one of the key challenges of system-on-achip
(SOC) implementation in nanoscale CMOS processes. The on-chip ESD protection circuit for mixed-voltage I/O interfaces should
meet the gate-oxide reliability constraints and prevent the undesired leakage current paths. This paper presents an overview on the design
concept and circuit implementations of ESD protection designs for mixed-voltage I/O interfaces with only low-voltage thin-oxide CMOS
transistors. Especially, the ESD protection designs for mixed-voltage I/O interfaces with ESD bus and high-voltage-tolerant power-rail
ESD clamp circuits are presented and discussed.
Overview and design of mixed-voltage I/O buffers with low-voltage thin-oxide CMOS transistors
Ming-Dou Ker, S.-L. Chen, and C.-S. Tsai, “Overview and design of mixed-voltage I/O buffers with low-voltage thin-oxide CMOS transistors,” IEEE Trans. on Circuits and Systems I: Regular Papers, vol. 53, no. 9, pp. 1934-1945, Sep. 2006.
Abstract
Overview on the prior designs of the mixed-voltage I/O buffers is provided in this work. A new 2.5/5-V mixed-voltage I/O buffer realized with only thin gate-oxide devices is proposed. The new proposed mixed-voltage I/O buffer with simpler dynamic n-well bias circuit and gate-tracking circuit can prevent the undesired leakage current paths and the gate-oxide reliability problem, which occur in the conventional CMOS I/O buffer. The new mixed-voltage I/O buffer has been fabricated and verified in a 0.25- m CMOS process to serve 2.5/5-V I/O interface. Besides, another 2.5/5-V mixed-voltage I/O buffer without the subthreshold leakage problem for high-speed applications is also presented in this work. The speed, power consumption, area, and noise among these mixed-voltage I/O buffers are also compared and discussed. The new proposed mixed-voltage I/O buffers can be easily scaled toward 0.18-um (or below) CMOS processes to serve other mixed-voltage I/O interfaces, such as 1.8/3.3-V interface.
Overview on electrostatic discharge protection designs for mixed-voltage I/O interfaces: design concept and circuit implementations
Ming-Dou Ker and K.-H. Lin, Overview on electrostatic discharge protection designs for mixed-voltage I/O interfaces: design concept and circuit implementations, IEEE Trans. on Circuits and Systems I: Regular Papers, vol. 53, no. 2, pp. 235-246, Feb. 2006
ABSTRACT
Electrostatic discharge (ESD) protection design for mixed-voltage I/O interfaces has been one of the key challenges of system-on-a-chip (SOC) implementation in nano-scale CMOSprocesses. The on-chip ESD protection circuit for mixed-voltage I/O interfaces should meet the gate-oxide reliability constraints and prevent the undesired leakage current paths. This paper presents an overview on the design concept and circuit implementations of the ESD protection designs for mixed-voltage I/O interfaces without using the additional thick gate-oxide process. The ESD design constraints in mixed-voltage I/O interfaces, the classification and analysis of ESD protection designs for mixed-voltage I/O interfaces, and the designs of high-voltage-tolerant power-rail ESD clamp circuit are presented and discussed.
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