『三味书屋』元旦送礼之四：The Kluwer 2002～2004(模拟部分)(H～M)

benemale

	High Frequency Continuous Time Filters in Digital CMOS Processes Pavan, Shanthi, Tsividis, Yannis 2000, 240 p., Hardcover ISBN: 978-0-7923-7773-3 Order now, and we will ship when available. (Your credit card will not be charged until we ship).
	$176.00

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About this book
There is an ever-increasing trend towards putting entire systems on a single chip. This means that Analog circuits will have to coexist on the same substrate along with massive digital systems. Since technologies are optimized with these digital systems in mind, designers will have to make do with standard CMOS processes in the years to come. Filters form important blocks in applications ranging from computer disc-drive chips to radio transceivers.
High Frequency Continuous Time Filters in Digital CMOS Processes addresses the theoretical and practical problems encountered in the design of robust, programmable continuous-time filters with very high bandwidths, implemented in low-cost digital CMOS technologies.
A high performance programmable filter architecture, called `constant-capacitance scaling', is discussed in detail. This technique has the potential for very high-speed operation, and ensures that frequency response shape, noise and dynamic range are maintained as bandwidth is programmed.
High Frequency Continuous Time Filters in Digital CMOS Processes will be of interest to analog circuit designers as well as researchers interested in filter and network theory.

[ 本帖最后由 benemale 于 2008-1-7 23:55 编辑 ]

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	High Performance Memory Testing Design Principles, Fault Modeling and Self-Test Series: Frontiers in Electronic Testing , Vol. 22A Adams, R. Dean 2002, 268 p., Hardcover ISBN: 978-1-4020-7255-0 Ships in 3 - 5 business days
	$139.00

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Design and test are considered jointly in this book since knowledge of one without the other is insufficient for the task of having high quality memories. Knowledge of memory design is required to understand test. An understanding of test is required to have effective built-in self-test implementations. A poor job can be done on any of these pieces resulting in a memory that passes test but which is not actually good. The relentless press of Moore's law drives more and more bits onto a single chip. The large number of bits means that methods that were "gotten away with" in the past will no longer be sufficient. Because the number of bits is so large, fine nuances of fails that were rarely seen previously now will happen regularly on most chips. These subtle fails must be caught or else quality will suffer severely.
Are memory applications more critical than they have been in the past? Yes, but even more critical is the number of designs and the sheer number of bits on each design. It is assured that catastrophes, which were avoided in the past because memories were small, will easily occur if the design and test engineers do not do their jobs very carefully.
High Performance Memory Testing: Design Principles, Fault Modeling and Self Test is based on the author's 20 years of experience in memory design, memory reliability development and memory self test.
High Performance Memory Testing: Design Principles, Fault Modeling and Self Test is written for the professional and the researcher to help them understand the memories that are being tested.

Written for:
Professionals, researchers

[ 本帖最后由 benemale 于 2008-1-7 23:56 编辑 ]

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	High-Speed CMOS Circuits for Optical Receivers Savoj, Jafar, Razavi, Behzad 2001, 144 p., Hardcover ISBN: 978-0-7923-7388-9 Ships in 3 - 5 business days
	$149.00

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The exponential growth of the number of internet nodes has suddenly created a widespread demand for high-speed optical and electronic devices, circuits, and systems. The new optical revolution has replaced modular, general-purpose building blocks by end-to-end solutions. Greater levels of integration on a single chip enable higher performance and lower cost. The mainstream VLSI technologies such as BiCmos and CMOS continue to take over the territories thus far claimed by GaAs and InP devices. This calls for an up-to-date book describing the design of high-speed electronic circuits for optical communication using modern techniques in a low-cost CMOS process.
High-Speed CMOS Circuits for Optical Receivers covers the design of the world's first and second 10 Gb/s clock and data recovery circuits fabricated in a pure CMOS process. The second prototype meets some of the critical requirements recommended by the SONET OC-192 standard. The clock and data recovery circuits consume a power several times lower than in prototypes built in other fabrication processes.
High-Speed CMOS Circuits for Optical Receivers describes novel techniques for implementation of such high-speed, high-performance circuits in a pure CMOS process.
High-Speed CMOS Circuits for Optical Receivers is written for researchers and students interested in high-speed and mixed-mode circuit design with focus on CMOS circuit techniques. Designers working on various high-speed circuit projects for data communication, including optical com., giga bit ethernet will also find it of interest.

[ 本帖最后由 benemale 于 2008-1-7 23:56 编辑 ]

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	IC Interconnect Analysis Celik, Mustafa, Pileggi, Larry, Odabasioglu, Altan 2002, 320 p., Hardcover ISBN: 978-1-4020-7075-4 Ships in 3 - 5 business days
	$149.00

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As integrated circuit (IC) feature sizes scaled below a quarter of a micron, thereby defining the deep submicron (DSM) era, there began a gradual shift in the impact on performance due to the metal interconnections among the active circuit components. Once viewed as merely parasitics in terms of their relevance to the overall circuit behavior, the interconnect can now have a dominant impact on the IC area and performance. Beginning in the late 1980's there was significant research toward better modeling and characterization of the resistance, capacitance and ultimately the inductance of on-chip interconnect.
IC Interconnect Analysis covers the state-of-the-art methods for modeling and analyzing IC interconnect based on the past fifteen years of research. This is done at a level suitable for most practitioners who work in the semiconductor and electronic design automation fields, but also includes significant depth for the research professionals who will ultimately extend this work into other areas and applications.
IC Interconnect Analysis begins with an in-depth coverage of delay metrics, including the ubiquitous Elmore delay and its many variations. This is followed by an outline of moment matching methods, calculating moments efficiently, and Krylov subspace methods for model order reduction. The final two chapters describe how to interface these reduced-order models to circuit simulators and gate-level timing analyzers respectively.
IC Interconnect Analysis is written for CAD tool developers, IC designers and graduate students.

[ 本帖最后由 benemale 于 2008-1-7 23:57 编辑 ]

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	Interconnection Noise in VLSI Circuits Moll, Francesc, Roca, Miquel 2004, 200 p., Hardcover ISBN: 978-1-4020-7733-3 This item usually ships in 3-4 weeks.
	$159.00

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Interconnection Noise in VLSI Circuits addresses two main problems with interconnections at the chip and package level: crosstalk and simultaneous switching noise. It is intended to provide the notions required for understanding the problem of modeling starting from physical arguments, so that it is possible to select an appropriate interconnection model that is both simple and accurate for the type of problems arising. Later, simple models of crosstalk and switching noise are used to give an intuitive understanding of these problems. Finally, some verification and test issues related to interconnection noise are discussed. Throughout the book, the examples used to illustrate the discussion are based on digital CMOS circuits, but the general treatment of the problems is made from a fundamental point of view, so that the discussion can be applied to different technologies. The book should be of interest to chip designers, especially for digital designers dealing with interconnect problems who want a deeper explanation of these phenomena. In this sense, the book's orientation is towards giving general information rather than being a compilation of practical cases. Each chapter contains a list of references for the topics dealt with, both recent and classic ones.
Written for:
Chip designers, digital designers dealing with interconnect problems

[ 本帖最后由 benemale 于 2008-1-7 23:57 编辑 ]

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	Low-Power Design Techniques and CAD Tools for Analog and RF Integrated Circuits Wambacq, Piet; Gielen, Georges; Gerrits, John (Eds.) 2001, 328 p., Hardcover ISBN: 978-0-7923-7432-9 Ships in 3 - 5 business days
	$209.00

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Modern System-on-Chip designs are increasingly mixed-signal designs that require efficient systematic design methodologies and supporting computer-aided design (CAD) tools to manage the design complexity in the available design time, that is ever decreasing due to tightening time-to-market constraints. The purpose of Low-Power Design Techniques and CAD Tools for Analog and RF Integrated Circuits is to provide an overview of very recent research results that have been achieved as part of the Low-Power Initiative of the European Union, in the field of analog, RF and mixed-signal design methodologies and CAD tools. It is a representative sampling of the current state of the art in this area, with special focus on low-power design methodologies and tools for analog and RF circuits and architectures. Concrete designs, mainly for telecommunication applications, such as low-noise amplifiers, oscillators, filters, but also complete transceiver front-ends, are discussed and analyzed in a methodological way, and their modeling and simulation, both at the circuit level and at the architectural level, are treated. In this way, the eleven contributions of this book combine in a unique way designs with methodologies and CAD that will be interesting to designers and CAD developers, both in industry and academia.

[ 本帖最后由 benemale 于 2008-1-7 23:59 编辑 ]

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	Low Voltage, Low Power CMOS Current Conveyors Ferri, Giuseppe, Guerrini, Nicola C. 2003, 226 p., Hardcover ISBN: 978-1-4020-7486-8 Ships in 3 - 5 business days
	$179.00

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Research in analog integrated circuits has recently gone in the direction of low-voltage (LV), low-power (LP) design, especially in the environment of portable systems where a low supply voltage, given by a single-cell battery, is used. These LV circuits have to show a reduced power consumption to maintain a longer battery lifetime as well. In this area, traditional voltage-mode techniques are going to be substituted by the current-mode approach, which has the recognized advantage to overcome the gain-bandwidth product limitation, typical of operational amplifiers. Then they do not require high voltage gains and have good performance in terms of speed, bandwidth and accuracy. Inside the current-mode architectures, the current-conveyor (CCII) can be considered the basic circuit block because all the active devices can be made of a suitable connection of one or two CCIIs. CCII is particularly attractive in portable systems, where LV LP constraints have to be taken into account. In fact, it suffers less from the limitation of low current utilisation, while showing full dynamic characteristics at reduced supplies (especially CMOS version) and good high frequency performance. Recent advances in integrated circuit technology have also highlighted the usefulness of CCII solutions in a large number of signal processing applications.
In Low Voltage, Low Power CMOS Current Conveyors, the authors start by giving a brief history of the first and second generation CC. Then, the second generation current-conveyor (CCII) will be considered as a building block in the main active feedback devices and in the implementation of simple analog functions, as an alternative to OA. In the next chapters, the design of CCII topologies will be considered, together with a further look into CCII modern solutions and future trends. The authors will, therefore, describe LV LP CCII implementations, their evolution towards differential and generalized topologies, and new possible CCII applications in some basic analog functions such as filters, impedance simulators and converters, oscillators, among others.
Being a concise and modern book on current conveyors, Low Voltage, Low Power CMOS Current Conveyors considers these kinds of devices both in a general environment and for low-voltage low-power applications. This book can constitute an excellent reference for analog designers and researchers and is suitable for use as a textbook in an advanced course on Microelectronics.
Written for:
Analog designers, researchers

[ 本帖最后由 benemale 于 2008-1-8 00:00 编辑 ]

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	Mixed Signal VLSI Wireless Design Circuits and Systems Farag, Emad N., Elmasry, Mohamed I. 1999, 352 p., Hardcover ISBN: 978-0-7923-8687-2 Ships in 3 - 5 business days
	$149.00

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The wireless revolution has come upon us swiftly and powerfully.
Today one of the most challenging areas for VLSI designers is VLSI circuit and system design for wireless applications. The design of a cellular radio system involves several engineering disciplines ranging from communication theory and digital signal processing to high frequency semiconductor technology and circuit design. Furthermore, the new generation of wireless systems, which includes multimedia, puts severe constraints on performance, cost, size, power and energy.
VLSI designers now need to understand both wireless communication and mixed signal design. Mixed Signal VLSI Wireless Design: Circuits and Systems provides the designer with an overview of wireless communication systems, followed by a detailed treatment of related topics such as the mobile radio, digital modulation and schemes, spread spectrum and receiver architectures.
The second half of the book deals with VLSI design issues related to mixed-signal design. These include analog-to-digital conversion, transceiver design, digital low-power techniques, amplifier design, phase-locked loops and frequency synthesizers.
Mixed Signal VLSI Wireless Design: Circuits and Systems is written for use in advanced level courses and also serves as a basic reference for professional engineers.

[ 本帖最后由 benemale 于 2008-1-8 00:01 编辑 ]

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	MOSFET Modeling and BSIM3 User's Guide Yuhua Cheng, Chenming Hu 1999, 484 p., Hardcover ISBN: 978-0-7923-8575-2 Ships in 3 - 5 business days
	$235.00

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Circuit simulation is essential in integrated circuit design, and the accuracy of circuit simulation depends on the accuracy of the transistor model. BSIM3v3 (BSIM for Berkeley Short-channel IGFET Model) has been selected as the first MOSFET model for standardization by the Compact Model Council, a consortium of leading companies in semiconductor and design tools.
In the next few years, many fabless and integrated semiconductor companies are expected to switch from dozens of other MOSFET models to BSIM3. This will require many device engineers and most circuit designers to learn the basics of BSIM3.
MOSFET Modeling & BSIM3 User's Guide explains the detailed physical effects that are important in modeling MOSFETs, and presents the derivations of compact model expressions so that users can understand the physical meaning of the model equations and parameters.
It is the first book devoted to BSIM3. It treats the BSIM3 model in detail as used in digital, analog and RF circuit design. It covers the complete set of models, i.e., I-V model, capacitance model, noise model, parasitics model, substrate current model, temperature effect model and non quasi-static model.
MOSFET Modeling & BSIM3 User's Guide not only addresses the device modeling issues but also provides a user's guide to the device or circuit design engineers who use the BSIM3 model in digital/analog circuit design, RF modeling, statistical modeling, and technology prediction.
This book is written for circuit designers and device engineers, as well as device scientists worldwide. It is also suitable as a reference for graduate courses and courses in circuit design or device modelling. Furthermore, it can be used as a textbook for industry courses devoted to BSIM3.
MOSFET Modeling & BSIM3 User's Guide is comprehensive and practical. It is balanced between the background information and advanced discussion of BSIM3. It is helpful to experts and students alike.

[ 本帖最后由 benemale 于 2008-1-8 00:02 编辑 ]

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	Multi-GHz Frequency Synthesis & Division Frequency Synthesizer Design for 5 GHz Wireless LAN Systems Rategh, Hamid R., Lee, Thomas H. 2001, 168 p., Hardcover ISBN: 978-0-7923-7533-3 Ships in 3 - 5 business days
	$159.00

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There has been an increasing demand for Wireless Local Area Network (WLAN) systems in the past few years. New frequency bands are allocated and new standards are being developed to accommodate higher data rates. The fast trend of CMOS scaling has provided an opportunity for the development of low cost integrated WLAN systems.
Frequency synthesizers are one of the main building blocks of wireless transceivers. The high frequency digital frequency dividers in a phase-locked loop (PLL) based frequency synthesizer are among the most challenging blocks to design and usually account for a large percentage of the synthesizer total power dissipation. The successful design and integration of a high frequency PLL demands a comprehensive understanding of wireless systems, RF circuits, and loop stability issues.
Multi-GHz Frequency Synthesis & Division starts with an overview of WLAN systems and reviews the WLAN market and standards. It then studies PLLs as an essential building block of WLAN receivers, and provides guidelines and engineering recipes for the design of loop filters in high frequency PLLs. Additionally, the book investigates different analog and digital frequency division techniques and introduces injection-locked frequency dividers (ILFDs) as an alternative for conventional frequency dividers. Finally, the book demonstrates a successful design of a fully integrated CMOS frequency synthesizer for a 5 GHz WLAN receiver.
Multi-GHz Frequency Synthesis & Division will be of interest to RF and high-speed analog circuit designers and students as well as wireless engineers.

[ 本帖最后由 benemale 于 2008-1-8 00:03 编辑 ]