不知道如何在设计中例化io_pad

郑伟

coolbear2021 发表于 2021-11-23 13:27
log里怎么会有"\037777777640"这种东西呀？好像乱码一样的，没有见过这种log。
...

大神，我解决了，是因为有空格，我之前复制的时候，那些空格也复制了，空格格式不对，之后改的时候，我也没改空格，觉得你那样写挺好看的整齐，就是把字母标点在原位置改了。刚才我把空格都删了就好了

郑伟

coolbear2021 发表于 2021-11-23 13:27
log里怎么会有"\037777777640"这种东西呀？好像乱码一样的，没有见过这种log。
...

大神，你会综合的东西吗，我以前都是stdcell综合，没有问题，这次加了io以后综合出来了警告和违例

ahzhangyq

你好，能帮我看下吗？照着写的出了很多问题。
module binmp(
    input     wire    pad_Clk,

    input     wire    pad_Rst_n,

    input     wire    [3:0] pad_hidden_in,

    input     wire    [5:0] pad_W2,

    input     wire    pad_en,

    output  wire    [9:0] pad_out
);

wire    pad_Clk;

wire    pad_Rst_n;

wire    [3:0] pad_hidden_in;

wire    [5:0] pad_W2;

wire    pad_en;

wire    [9:0] pad_out;

Binary_Mult    u_Binary_Mult(
    .Clk(pad_Clk),

    .Rst_n(pad_Rst_n),

    .hidden_in(pad_hidden_in),

    .W2(pad_W2),

    .en(pad_en),

    .out(pad_out)
);

//iopad:    PDDW0204SCDG (I,DS,OEN,PAD,C,PE,IE);
//input:    (.I(1'b0),.DS(1'b0),.OEN(1'b1),.PAD(pad_),.C(),.PE(1'b0),.IE(1'b1));
//output:    (.I(),.DS(1'b1),.OEN(1'b0),.PAD(pad_),.C(),.PE(1'b1),.IE(1'b1));

// input
PDDW0204SCDG    clk_iopad             (.I(1'b0),.DS(1'b0),.OEN(1'b1),.PAD(pad_Clk),            .C(Clk),            .PE(1'b0),.IE(1'b1));
PDDW0204SCDG    Rst_n_iopad         (.I(1'b0),.DS(1'b0),.OEN(1'b1),.PAD(pad_Rst_n),            .C(Rst_n),            .PE(1'b0),.IE(1'b1));
PDDW0204SCDG    hidden_in_iopad0     (.I(1'b0),.DS(1'b0),.OEN(1'b1),.PAD(pad_hidden_in[0]),    .C(hidden_in[0]),    .PE(1'b0),.IE(1'b1));
PDDW0204SCDG    hidden_in_iopad1     (.I(1'b0),.DS(1'b0),.OEN(1'b1),.PAD(pad_hidden_in[1]),    .C(hidden_in[1]),    .PE(1'b0),.IE(1'b1));
PDDW0204SCDG    hidden_in_iopad2     (.I(1'b0),.DS(1'b0),.OEN(1'b1),.PAD(pad_hidden_in[2]),    .C(hidden_in[2]),    .PE(1'b0),.IE(1'b1));
PDDW0204SCDG    hidden_in_iopad3     (.I(1'b0),.DS(1'b0),.OEN(1'b1),.PAD(pad_hidden_in[3]),    .C(hidden_in[3]),    .PE(1'b0),.IE(1'b1));
PDDW0204SCDG    W2_iopad0             (.I(1'b0),.DS(1'b0),.OEN(1'b1),.PAD(pad_W2[0]),            .C(W2[0]),            .PE(1'b0),.IE(1'b1));
PDDW0204SCDG    W2_iopad1             (.I(1'b0),.DS(1'b0),.OEN(1'b1),.PAD(pad_W2[1]),            .C(W2[1]),            .PE(1'b0),.IE(1'b1));
PDDW0204SCDG    W2_iopad2             (.I(1'b0),.DS(1'b0),.OEN(1'b1),.PAD(pad_W2[2]),            .C(W2[2]),            .PE(1'b0),.IE(1'b1));
PDDW0204SCDG    W2_iopad3             (.I(1'b0),.DS(1'b0),.OEN(1'b1),.PAD(pad_W2[3]),            .C(W2[3]),            .PE(1'b0),.IE(1'b1));
PDDW0204SCDG    W2_iopad4             (.I(1'b0),.DS(1'b0),.OEN(1'b1),.PAD(pad_W2[4]),            .C(W2[4]),            .PE(1'b0),.IE(1'b1));
PDDW0204SCDG    W2_iopad5             (.I(1'b0),.DS(1'b0),.OEN(1'b1),.PAD(pad_W2[5]),            .C(W2[5]),            .PE(1'b0),.IE(1'b1));
PDDW0204SCDG    en_iopad              (.I(1'b0),.DS(1'b0),.OEN(1'b1),.PAD(pad_en),            .C(en),                .PE(1'b0),.IE(1'b1));
// output
PDDW0204SCDG    out_iopad0             (.I(out[0]),.DS(1'b1),.OEN(1'b0),.PAD(pad_out[0]),        .C(),                .PE(1'b0),.IE(1'b0));
PDDW0204SCDG    out_iopad1             (.I(out[1]),.DS(1'b1),.OEN(1'b0),.PAD(pad_out[1]),        .C(),                .PE(1'b0),.IE(1'b0));
PDDW0204SCDG    out_iopad2             (.I(out[2]),.DS(1'b1),.OEN(1'b0),.PAD(pad_out[2]),        .C(),                .PE(1'b0),.IE(1'b0));
PDDW0204SCDG    out_iopad3             (.I(out[3]),.DS(1'b1),.OEN(1'b0),.PAD(pad_out[3]),        .C(),                .PE(1'b0),.IE(1'b0));
PDDW0204SCDG    out_iopad4             (.I(out[4]),.DS(1'b1),.OEN(1'b0),.PAD(pad_out[4]),        .C(),                .PE(1'b0),.IE(1'b0));
PDDW0204SCDG    out_iopad5             (.I(out[5]),.DS(1'b1),.OEN(1'b0),.PAD(pad_out[5]),        .C(),                .PE(1'b0),.IE(1'b0));
PDDW0204SCDG    out_iopad6             (.I(out[6]),.DS(1'b1),.OEN(1'b0),.PAD(pad_out[6]),        .C(),                .PE(1'b0),.IE(1'b0));
PDDW0204SCDG    out_iopad7             (.I(out[7]),.DS(1'b1),.OEN(1'b0),.PAD(pad_out[7]),        .C(),                .PE(1'b0),.IE(1'b0));
PDDW0204SCDG    out_iopad8             (.I(out[8]),.DS(1'b1),.OEN(1'b0),.PAD(pad_out[8]),        .C(),                .PE(1'b0),.IE(1'b0));
PDDW0204SCDG    out_iopad9             (.I(out[9]),.DS(1'b1),.OEN(1'b0),.PAD(pad_out[9]),        .C(),                .PE(1'b0),.IE(1'b0));

endmodule

错误问题
Compiling source file ./rtl/tpdn65lpnv2od3.v
Warning:  ./rtl/tpdn65lpnv2od3.v:53: the undeclared symbol 'PAD_i' assumed to have the default net type, which is 'wire'. (VER-936)
Warning:  ./rtl/tpdn65lpnv2od3.v:55: the undeclared symbol 'CO' assumed to have the default net type, which is 'wire'. (VER-936)
Warning:  ./rtl/tpdn65lpnv2od3.v:56: the undeclared symbol 'C_buf' assumed to have the default net type, which is 'wire'. (VER-936)
Warning:  ./rtl/tpdn65lpnv2od3.v:57: the undeclared symbol 'PUEN' assumed to have the default net type, which is 'wire'. (VER-936)
Warning:  ./rtl/tpdn65lpnv2od3.v:58: the undeclared symbol 'PU' assumed to have the default net type, which is 'wire'. (VER-936)
Warning:  ./rtl/tpdn65lpnv2od3.v:59: the undeclared symbol 'PSB' assumed to have the default net type, which is 'wire'. (VER-936)
Warning:  ./rtl/tpdn65lpnv2od3.v:60: the undeclared symbol 'PD' assumed to have the default net type, which is 'wire'. (VER-936)
Warning:  ./rtl/tpdn65lpnv2od3.v:61: the undeclared symbol 'PAD_q' assumed to have the default net type, which is 'wire'. (VER-936)
Warning:  ./rtl/tpdn65lpnv2od3.v:62: the undeclared symbol 'DS_tmp' assumed to have the default net type, which is 'wire'. (VER-936)
Error:  ./rtl/tpdn65lpnv2od3.v:69: case equality (===) is not supported by synthesis. (VER-189)
Warning:  ./rtl/tpdn65lpnv2od3.v:69: The construct '$test$plusargs system function' is not supported in synthesis; it is ignored. (VER-708)
Error:  ./rtl/tpdn65lpnv2od3.v:71: case equality (===) is not supported by synthesis. (VER-189)
Error:  ./rtl/tpdn65lpnv2od3.v:71: case equality (===) is not supported by synthesis. (VER-189)
Error:  ./rtl/tpdn65lpnv2od3.v:71: case equality (===) is not supported by synthesis. (VER-189)
Error:  ./rtl/tpdn65lpnv2od3.v:73: case equality (===) is not supported by synthesis. (VER-189)
Error:  ./rtl/tpdn65lpnv2od3.v:84: case equality (===) is not supported by synthesis. (VER-189)
Warning:  ./rtl/tpdn65lpnv2od3.v:96: The construct 'specify' is not supported in synthesis; it is ignored. (VER-708)
Warning:  ./rtl/tpdn65lpnv2od3.v:121: the undeclared symbol 'PAD_i' assumed to have the default net type, which is 'wire'. (VER-936)
Warning:  ./rtl/tpdn65lpnv2od3.v:123: the undeclared symbol 'CO' assumed to have the default net type, which is 'wire'. (VER-936)
Warning:  ./rtl/tpdn65lpnv2od3.v:124: the undeclared symbol 'C_buf' assumed to have the default net type, which is 'wire'. (VER-936)
Warning:  ./rtl/tpdn65lpnv2od3.v:125: the undeclared symbol 'PUEN' assumed to have the default net type, which is 'wire'. (VER-936)
Warning:  ./rtl/tpdn65lpnv2od3.v:126: the undeclared symbol 'PU' assumed to have the default net type, which is 'wire'. (VER-936)
Warning:  ./rtl/tpdn65lpnv2od3.v:127: the undeclared symbol 'PSB' assumed to have the default net type, which is 'wire'. (VER-936)
Warning:  ./rtl/tpdn65lpnv2od3.v:128: the undeclared symbol 'PD' assumed to have the default net type, which is 'wire'. (VER-936)
Warning:  ./rtl/tpdn65lpnv2od3.v:129: the undeclared symbol 'PAD_q' assumed to have the default net type, which is 'wire'. (VER-936)
Warning:  ./rtl/tpdn65lpnv2od3.v:130: the undeclared symbol 'DS_tmp' assumed to have the default net type, which is 'wire'. (VER-936)
Error:  ./rtl/tpdn65lpnv2od3.v:137: case equality (===) is not supported by synthesis. (VER-189)
Warning:  ./rtl/tpdn65lpnv2od3.v:137: The construct '$test$plusargs system function' is not supported in synthesis; it is ignored. (VER-708)
Error:  ./rtl/tpdn65lpnv2od3.v:139: case equality (===) is not supported by synthesis. (VER-189)
Error:  ./rtl/tpdn65lpnv2od3.v:139: case equality (===) is not supported by synthesis. (VER-189)
Error:  ./rtl/tpdn65lpnv2od3.v:139: case equality (===) is not supported by synthesis. (VER-189)
Error:  ./rtl/tpdn65lpnv2od3.v:141: case equality (===) is not supported by synthesis. (VER-189)
Error:  ./rtl/tpdn65lpnv2od3.v:152: case equality (===) is not supported by synthesis. (VER-189)
Warning:  ./rtl/tpdn65lpnv2od3.v:164: The construct 'specify' is not supported in synthesis; it is ignored. (VER-708)
Warning:  ./rtl/tpdn65lpnv2od3.v:189: the undeclared symbol 'PAD_i' assumed to have the default net type, which is 'wire'. (VER-936)
Warning:  ./rtl/tpdn65lpnv2od3.v:191: the undeclared symbol 'CO' assumed to have the default net type, which is 'wire'. (VER-936)
Warning:  ./rtl/tpdn65lpnv2od3.v:192: the undeclared symbol 'C_buf' assumed to have the default net type, which is 'wire'. (VER-936)
Warning:  ./rtl/tpdn65lpnv2od3.v:193: the undeclared symbol 'PUEN' assumed to have the default net type, which is 'wire'. (VER-936)
Warning:  ./rtl/tpdn65lpnv2od3.v:194: the undeclared symbol 'PU' assumed to have the default net type, which is 'wire'. (VER-936)
Warning:  ./rtl/tpdn65lpnv2od3.v:195: the undeclared symbol 'PSB' assumed to have the default net type, which is 'wire'. (VER-936)
Warning:  ./rtl/tpdn65lpnv2od3.v:196: the undeclared symbol 'PD' assumed to have the default net type, which is 'wire'. (VER-936)
Warning:  ./rtl/tpdn65lpnv2od3.v:197: the undeclared symbol 'PAD_q' assumed to have the default net type, which is 'wire'. (VER-936)
Warning:  ./rtl/tpdn65lpnv2od3.v:198: the undeclared symbol 'DS_tmp' assumed to have the default net type, which is 'wire'. (VER-936)
Error:  ./rtl/tpdn65lpnv2od3.v:205: case equality (===) is not supported by synthesis. (VER-189)
Warning:  ./rtl/tpdn65lpnv2od3.v:205: The construct '$test$plusargs system function' is not supported in synthesis; it is ignored. (VER-708)
Error:  ./rtl/tpdn65lpnv2od3.v:207: case equality (===) is not supported by synthesis. (VER-189)
Error:  ./rtl/tpdn65lpnv2od3.v:207: case equality (===) is not supported by synthesis. (VER-189)
Error:  ./rtl/tpdn65lpnv2od3.v:207: case equality (===) is not supported by synthesis. (VER-189)
Error:  ./rtl/tpdn65lpnv2od3.v:209: case equality (===) is not supported by synthesis. (VER-189)
Error:  ./rtl/tpdn65lpnv2od3.v:220: case equality (===) is not supported by synthesis. (VER-189)
Warning:  ./rtl/tpdn65lpnv2od3.v:232: The construct 'specify' is not supported in synthesis; it is ignored. (VER-708)
Warning:  ./rtl/tpdn65lpnv2od3.v:257: the undeclared symbol 'PAD_i' assumed to have the default net type, which is 'wire'. (VER-936)
Warning:  ./rtl/tpdn65lpnv2od3.v:259: the undeclared symbol 'CO' assumed to have the default net type, which is 'wire'. (VER-936)
Warning:  ./rtl/tpdn65lpnv2od3.v:260: the undeclared symbol 'C_buf' assumed to have the default net type, which is 'wire'. (VER-936)
Warning:  ./rtl/tpdn65lpnv2od3.v:261: the undeclared symbol 'PUEN' assumed to have the default net type, which is 'wire'. (VER-936)
Warning:  ./rtl/tpdn65lpnv2od3.v:262: the undeclared symbol 'PU' assumed to have the default net type, which is 'wire'. (VER-936)
Warning:  ./rtl/tpdn65lpnv2od3.v:263: the undeclared symbol 'PSB' assumed to have the default net type, which is 'wire'. (VER-936)
Warning:  ./rtl/tpdn65lpnv2od3.v:264: the undeclared symbol 'PD' assumed to have the default net type, which is 'wire'. (VER-936)
Warning:  ./rtl/tpdn65lpnv2od3.v:265: the undeclared symbol 'PAD_q' assumed to have the default net type, which is 'wire'. (VER-936)
Warning:  ./rtl/tpdn65lpnv2od3.v:266: the undeclared symbol 'DS_tmp' assumed to have the default net type, which is 'wire'. (VER-936)
Error:  ./rtl/tpdn65lpnv2od3.v:273: case equality (===) is not supported by synthesis. (VER-189)
Warning:  ./rtl/tpdn65lpnv2od3.v:273: The construct '$test$plusargs system function' is not supported in synthesis; it is ignored. (VER-708)
Error:  ./rtl/tpdn65lpnv2od3.v:275: case equality (===) is not supported by synthesis. (VER-189)
Error:  Too many errors; can't continue. (VER-40)
*** Presto compilation terminated with 21 errors. ***
Running PRESTO HDLC
Error:  ./rtl/binmp.v:33: Type query about dimensions or access by indexing requires an array reference as the first argument. (ELAB-400)
*** Presto compilation terminated with 1 errors. ***
Error: Current design is not defined. (UID-4)
Error: Current design is not defined. (UID-4)
Error: Current design is not defined. (UID-4)
Error: Can't find object 'pad_Clk'. (UID-109)
Error: Value for list 'source_objects' must have 1 elements. (CMD-036)
Error: Current design is not defined. (UID-4)
Error: Can't find object 'pad_Clk'. (UID-109)
Error: Value for list 'object_list' must have 1 elements. (CMD-036)
Error: Current design is not defined. (UID-4)
Error: Can't find clock 'pad_Clk'. (UID-109)
Error: Value for list 'object_list' must have 1 elements. (CMD-036)
Error: Current design is not defined. (UID-4)
Error: Can't find clock 'pad_Clk'. (UID-109)
Error: Value for list 'object_list' must have 1 elements. (CMD-036)
Error: Current design is not defined. (UID-4)
Error: Can't find clock 'pad_Clk'. (UID-109)
Error: Value for list 'clock_list' must have 1 elements. (CMD-036)
Error: Current design is not defined. (UID-4)
Error: Can't find ports matching '*'. (UID-109)
Error: Value for list 'objects' must have 1 elements. (CMD-036)
Error: Current design is not defined. (UID-4)
Error: Current design is not defined. (UID-4)
Error: Can't find clock 'pad_Clk'. (UID-109)
Error: Value for list '-clock' must have 1 elements. (CMD-036)
Error: Value for list 'port_pin_list' must have 1 elements. (CMD-036)
Error: Current design is not defined. (UID-4)
Error: Current design is not defined. (UID-4)
Error: Can't find clock 'pad_Clk'. (UID-109)
Error: Value for list '-clock' must have 1 elements. (CMD-036)
Error: Value for list 'port_pin_list' must have 1 elements. (CMD-036)
Error: Current design is not defined. (UID-4)
Error: Current design is not defined. (UID-4)
Error: Can't find object 'clk_iopad'. (UID-109)
Error: Current design is not defined. (UID-4)
Error: Can't find object 'Rst_n_iopad'. (UID-109)
Error: Current design is not defined. (UID-4)
Error: Can't find object 'hidden_in_iopad0'. (UID-109)
Error: Current design is not defined. (UID-4)
Error: Can't find object 'hidden_in_iopad1'. (UID-109)
Error: Current design is not defined. (UID-4)
Error: Can't find object 'hidden_in_iopad2'. (UID-109)
Error: Current design is not defined. (UID-4)
Error: Can't find object 'hidden_in_iopad3'. (UID-109)
Error: Current design is not defined. (UID-4)
Error: Can't find object 'W2_iopad0'. (UID-109)
Error: Current design is not defined. (UID-4)
Error: Can't find object 'W2_iopad1'. (UID-109)
Error: Current design is not defined. (UID-4)
Error: Can't find object 'W2_iopad2'. (UID-109)
Error: Current design is not defined. (UID-4)
Error: Can't find object 'W2_iopad3'. (UID-109)
Error: Current design is not defined. (UID-4)
Error: Can't find object 'W2_iopad4'. (UID-109)
Error: Current design is not defined. (UID-4)
Error: Can't find object 'W2_iopad5'. (UID-109)
Error: Current design is not defined. (UID-4)
Error: Can't find object 'en_iopad'. (UID-109)
Error: Current design is not defined. (UID-4)
Error: Can't find object 'out_iopad0'. (UID-109)
Error: Current design is not defined. (UID-4)
Error: Can't find object 'out_iopad1'. (UID-109)
Error: Current design is not defined. (UID-4)
Error: Can't find object 'out_iopad2'. (UID-109)
Error: Current design is not defined. (UID-4)
Error: Can't find object 'out_iopad3'. (UID-109)
Error: Current design is not defined. (UID-4)
Error: Can't find object 'out_iopad4'. (UID-109)
Error: Current design is not defined. (UID-4)
Error: Can't find object 'out_iopad5'. (UID-109)
Error: Current design is not defined. (UID-4)
Error: Can't find object 'out_iopad6'. (UID-109)
Error: Current design is not defined. (UID-4)
Error: Can't find object 'out_iopad7'. (UID-109)
Error: Current design is not defined. (UID-4)
Error: Can't find object 'out_iopad8'. (UID-109)
Error: Current design is not defined. (UID-4)
Error: Can't find object 'out_iopad9'. (UID-109)
Error: Value for list 'object_list' must have 1 elements. (CMD-036)
Information: Auto ungrouping of the design is disabled because the '-no_boundary_optimization' is used. (OPT-1316)
Warning: The value of variable 'compile_preserve_subdesign_interfaces' has been changed to true because '-no_boundary_optimization' is used. (OPT-133)
Information: Starting from 2013.12 release, constant propagation is enabled even when boundary optimization is disabled. (OPT-1318)
Error: Current design is not defined. (UID-4)
Error: Current design is not defined. (UID-4)
Error: Current design is not defined. (UID-4)
Error: Current design is not defined. (UID-4)

ahzhangyq

coolbear2021 发表于 2021-11-17 11:20
假定你的模块叫xxx，并且所有的port都要接到pad上，可以参考下面的代码。

你的代码里信号都是单向的，inpu ...

你好，能帮我看一下吗？ 照着写的，还是有问题。
代码文件为：

module binmp(
    input     wire    pad_Clk,

    input     wire    pad_Rst_n,

    input     wire    [3:0] pad_hidden_in,

    input     wire    [5:0] pad_W2,

    input     wire    pad_en,

    output  wire    [9:0] pad_out
);

wire    pad_Clk;

wire    pad_Rst_n;

wire    [3:0] pad_hidden_in;

wire    [5:0] pad_W2;

wire    pad_en;

wire    [9:0] pad_out;

Binary_Mult    u_Binary_Mult(
    .Clk(pad_Clk),

    .Rst_n(pad_Rst_n),

    .hidden_in(pad_hidden_in),

    .W2(pad_W2),

    .en(pad_en),

    .out(pad_out)
);

//iopad:    PDDW0204SCDG (I,DS,OEN,PAD,C,PE,IE);
//input:    (.I(1'b0),.DS(1'b0),.OEN(1'b1),.PAD(pad_),.C(),.PE(1'b0),.IE(1'b1));
//output:    (.I(),.DS(1'b1),.OEN(1'b0),.PAD(pad_),.C(),.PE(1'b1),.IE(1'b1));

// input
PDDW0204SCDG    clk_iopad             (.I(1'b0),.DS(1'b0),.OEN(1'b1),.PAD(pad_Clk),            .C(Clk),            .PE(1'b0),.IE(1'b1));
PDDW0204SCDG    Rst_n_iopad         (.I(1'b0),.DS(1'b0),.OEN(1'b1),.PAD(pad_Rst_n),            .C(Rst_n),            .PE(1'b0),.IE(1'b1));
PDDW0204SCDG    hidden_in_iopad0     (.I(1'b0),.DS(1'b0),.OEN(1'b1),.PAD(pad_hidden_in[0]),    .C(hidden_in[0]),    .PE(1'b0),.IE(1'b1));
PDDW0204SCDG    hidden_in_iopad1     (.I(1'b0),.DS(1'b0),.OEN(1'b1),.PAD(pad_hidden_in[1]),    .C(hidden_in[1]),    .PE(1'b0),.IE(1'b1));
PDDW0204SCDG    hidden_in_iopad2     (.I(1'b0),.DS(1'b0),.OEN(1'b1),.PAD(pad_hidden_in[2]),    .C(hidden_in[2]),    .PE(1'b0),.IE(1'b1));
PDDW0204SCDG    hidden_in_iopad3     (.I(1'b0),.DS(1'b0),.OEN(1'b1),.PAD(pad_hidden_in[3]),    .C(hidden_in[3]),    .PE(1'b0),.IE(1'b1));
PDDW0204SCDG    W2_iopad0             (.I(1'b0),.DS(1'b0),.OEN(1'b1),.PAD(pad_W2[0]),            .C(W2[0]),            .PE(1'b0),.IE(1'b1));
PDDW0204SCDG    W2_iopad1             (.I(1'b0),.DS(1'b0),.OEN(1'b1),.PAD(pad_W2[1]),            .C(W2[1]),            .PE(1'b0),.IE(1'b1));
PDDW0204SCDG    W2_iopad2             (.I(1'b0),.DS(1'b0),.OEN(1'b1),.PAD(pad_W2[2]),            .C(W2[2]),            .PE(1'b0),.IE(1'b1));
PDDW0204SCDG    W2_iopad3             (.I(1'b0),.DS(1'b0),.OEN(1'b1),.PAD(pad_W2[3]),            .C(W2[3]),            .PE(1'b0),.IE(1'b1));
PDDW0204SCDG    W2_iopad4             (.I(1'b0),.DS(1'b0),.OEN(1'b1),.PAD(pad_W2[4]),            .C(W2[4]),            .PE(1'b0),.IE(1'b1));
PDDW0204SCDG    W2_iopad5             (.I(1'b0),.DS(1'b0),.OEN(1'b1),.PAD(pad_W2[5]),            .C(W2[5]),            .PE(1'b0),.IE(1'b1));
PDDW0204SCDG    en_iopad              (.I(1'b0),.DS(1'b0),.OEN(1'b1),.PAD(pad_en),            .C(en),                .PE(1'b0),.IE(1'b1));
// output
PDDW0204SCDG    out_iopad0             (.I(out[0]),.DS(1'b1),.OEN(1'b0),.PAD(pad_out[0]),        .C(),                .PE(1'b0),.IE(1'b0));
PDDW0204SCDG    out_iopad1             (.I(out[1]),.DS(1'b1),.OEN(1'b0),.PAD(pad_out[1]),        .C(),                .PE(1'b0),.IE(1'b0));
PDDW0204SCDG    out_iopad2             (.I(out[2]),.DS(1'b1),.OEN(1'b0),.PAD(pad_out[2]),        .C(),                .PE(1'b0),.IE(1'b0));
PDDW0204SCDG    out_iopad3             (.I(out[3]),.DS(1'b1),.OEN(1'b0),.PAD(pad_out[3]),        .C(),                .PE(1'b0),.IE(1'b0));
PDDW0204SCDG    out_iopad4             (.I(out[4]),.DS(1'b1),.OEN(1'b0),.PAD(pad_out[4]),        .C(),                .PE(1'b0),.IE(1'b0));
PDDW0204SCDG    out_iopad5             (.I(out[5]),.DS(1'b1),.OEN(1'b0),.PAD(pad_out[5]),        .C(),                .PE(1'b0),.IE(1'b0));
PDDW0204SCDG    out_iopad6             (.I(out[6]),.DS(1'b1),.OEN(1'b0),.PAD(pad_out[6]),        .C(),                .PE(1'b0),.IE(1'b0));
PDDW0204SCDG    out_iopad7             (.I(out[7]),.DS(1'b1),.OEN(1'b0),.PAD(pad_out[7]),        .C(),                .PE(1'b0),.IE(1'b0));
PDDW0204SCDG    out_iopad8             (.I(out[8]),.DS(1'b1),.OEN(1'b0),.PAD(pad_out[8]),        .C(),                .PE(1'b0),.IE(1'b0));
PDDW0204SCDG    out_iopad9             (.I(out[9]),.DS(1'b1),.OEN(1'b0),.PAD(pad_out[9]),        .C(),                .PE(1'b0),.IE(1'b0));

endmodule


log文件为：
Compiling source file ./rtl/tpdn65lpnv2od3.v
Warning:  ./rtl/tpdn65lpnv2od3.v:53: the undeclared symbol 'PAD_i' assumed to have the default net type, which is 'wire'. (VER-936)
Warning:  ./rtl/tpdn65lpnv2od3.v:55: the undeclared symbol 'CO' assumed to have the default net type, which is 'wire'. (VER-936)
Warning:  ./rtl/tpdn65lpnv2od3.v:56: the undeclared symbol 'C_buf' assumed to have the default net type, which is 'wire'. (VER-936)
Warning:  ./rtl/tpdn65lpnv2od3.v:57: the undeclared symbol 'PUEN' assumed to have the default net type, which is 'wire'. (VER-936)
Warning:  ./rtl/tpdn65lpnv2od3.v:58: the undeclared symbol 'PU' assumed to have the default net type, which is 'wire'. (VER-936)
Warning:  ./rtl/tpdn65lpnv2od3.v:59: the undeclared symbol 'PSB' assumed to have the default net type, which is 'wire'. (VER-936)
Warning:  ./rtl/tpdn65lpnv2od3.v:60: the undeclared symbol 'PD' assumed to have the default net type, which is 'wire'. (VER-936)
Warning:  ./rtl/tpdn65lpnv2od3.v:61: the undeclared symbol 'PAD_q' assumed to have the default net type, which is 'wire'. (VER-936)
Warning:  ./rtl/tpdn65lpnv2od3.v:62: the undeclared symbol 'DS_tmp' assumed to have the default net type, which is 'wire'. (VER-936)
Error:  ./rtl/tpdn65lpnv2od3.v:69: case equality (===) is not supported by synthesis. (VER-189)
Warning:  ./rtl/tpdn65lpnv2od3.v:69: The construct '$test$plusargs system function' is not supported in synthesis; it is ignored. (VER-708)
Error:  ./rtl/tpdn65lpnv2od3.v:71: case equality (===) is not supported by synthesis. (VER-189)
Error:  ./rtl/tpdn65lpnv2od3.v:71: case equality (===) is not supported by synthesis. (VER-189)
Error:  ./rtl/tpdn65lpnv2od3.v:71: case equality (===) is not supported by synthesis. (VER-189)
Error:  ./rtl/tpdn65lpnv2od3.v:73: case equality (===) is not supported by synthesis. (VER-189)
Error:  ./rtl/tpdn65lpnv2od3.v:84: case equality (===) is not supported by synthesis. (VER-189)
Warning:  ./rtl/tpdn65lpnv2od3.v:96: The construct 'specify' is not supported in synthesis; it is ignored. (VER-708)
Warning:  ./rtl/tpdn65lpnv2od3.v:121: the undeclared symbol 'PAD_i' assumed to have the default net type, which is 'wire'. (VER-936)
Warning:  ./rtl/tpdn65lpnv2od3.v:123: the undeclared symbol 'CO' assumed to have the default net type, which is 'wire'. (VER-936)
Warning:  ./rtl/tpdn65lpnv2od3.v:124: the undeclared symbol 'C_buf' assumed to have the default net type, which is 'wire'. (VER-936)
Warning:  ./rtl/tpdn65lpnv2od3.v:125: the undeclared symbol 'PUEN' assumed to have the default net type, which is 'wire'. (VER-936)
Warning:  ./rtl/tpdn65lpnv2od3.v:126: the undeclared symbol 'PU' assumed to have the default net type, which is 'wire'. (VER-936)
Warning:  ./rtl/tpdn65lpnv2od3.v:127: the undeclared symbol 'PSB' assumed to have the default net type, which is 'wire'. (VER-936)
Warning:  ./rtl/tpdn65lpnv2od3.v:128: the undeclared symbol 'PD' assumed to have the default net type, which is 'wire'. (VER-936)
Warning:  ./rtl/tpdn65lpnv2od3.v:129: the undeclared symbol 'PAD_q' assumed to have the default net type, which is 'wire'. (VER-936)
Warning:  ./rtl/tpdn65lpnv2od3.v:130: the undeclared symbol 'DS_tmp' assumed to have the default net type, which is 'wire'. (VER-936)
Error:  ./rtl/tpdn65lpnv2od3.v:137: case equality (===) is not supported by synthesis. (VER-189)
Warning:  ./rtl/tpdn65lpnv2od3.v:137: The construct '$test$plusargs system function' is not supported in synthesis; it is ignored. (VER-708)
Error:  ./rtl/tpdn65lpnv2od3.v:139: case equality (===) is not supported by synthesis. (VER-189)
Error:  ./rtl/tpdn65lpnv2od3.v:139: case equality (===) is not supported by synthesis. (VER-189)
Error:  ./rtl/tpdn65lpnv2od3.v:139: case equality (===) is not supported by synthesis. (VER-189)
Error:  ./rtl/tpdn65lpnv2od3.v:141: case equality (===) is not supported by synthesis. (VER-189)
Error:  ./rtl/tpdn65lpnv2od3.v:152: case equality (===) is not supported by synthesis. (VER-189)
Warning:  ./rtl/tpdn65lpnv2od3.v:164: The construct 'specify' is not supported in synthesis; it is ignored. (VER-708)
Warning:  ./rtl/tpdn65lpnv2od3.v:189: the undeclared symbol 'PAD_i' assumed to have the default net type, which is 'wire'. (VER-936)
Warning:  ./rtl/tpdn65lpnv2od3.v:191: the undeclared symbol 'CO' assumed to have the default net type, which is 'wire'. (VER-936)
Warning:  ./rtl/tpdn65lpnv2od3.v:192: the undeclared symbol 'C_buf' assumed to have the default net type, which is 'wire'. (VER-936)
Warning:  ./rtl/tpdn65lpnv2od3.v:193: the undeclared symbol 'PUEN' assumed to have the default net type, which is 'wire'. (VER-936)
Warning:  ./rtl/tpdn65lpnv2od3.v:194: the undeclared symbol 'PU' assumed to have the default net type, which is 'wire'. (VER-936)
Warning:  ./rtl/tpdn65lpnv2od3.v:195: the undeclared symbol 'PSB' assumed to have the default net type, which is 'wire'. (VER-936)
Warning:  ./rtl/tpdn65lpnv2od3.v:196: the undeclared symbol 'PD' assumed to have the default net type, which is 'wire'. (VER-936)
Warning:  ./rtl/tpdn65lpnv2od3.v:197: the undeclared symbol 'PAD_q' assumed to have the default net type, which is 'wire'. (VER-936)
Warning:  ./rtl/tpdn65lpnv2od3.v:198: the undeclared symbol 'DS_tmp' assumed to have the default net type, which is 'wire'. (VER-936)
Error:  ./rtl/tpdn65lpnv2od3.v:205: case equality (===) is not supported by synthesis. (VER-189)
Warning:  ./rtl/tpdn65lpnv2od3.v:205: The construct '$test$plusargs system function' is not supported in synthesis; it is ignored. (VER-708)
Error:  ./rtl/tpdn65lpnv2od3.v:207: case equality (===) is not supported by synthesis. (VER-189)
Error:  ./rtl/tpdn65lpnv2od3.v:207: case equality (===) is not supported by synthesis. (VER-189)
Error:  ./rtl/tpdn65lpnv2od3.v:207: case equality (===) is not supported by synthesis. (VER-189)
Error:  ./rtl/tpdn65lpnv2od3.v:209: case equality (===) is not supported by synthesis. (VER-189)
Error:  ./rtl/tpdn65lpnv2od3.v:220: case equality (===) is not supported by synthesis. (VER-189)
Warning:  ./rtl/tpdn65lpnv2od3.v:232: The construct 'specify' is not supported in synthesis; it is ignored. (VER-708)
Warning:  ./rtl/tpdn65lpnv2od3.v:257: the undeclared symbol 'PAD_i' assumed to have the default net type, which is 'wire'. (VER-936)
Warning:  ./rtl/tpdn65lpnv2od3.v:259: the undeclared symbol 'CO' assumed to have the default net type, which is 'wire'. (VER-936)
Warning:  ./rtl/tpdn65lpnv2od3.v:260: the undeclared symbol 'C_buf' assumed to have the default net type, which is 'wire'. (VER-936)
Warning:  ./rtl/tpdn65lpnv2od3.v:261: the undeclared symbol 'PUEN' assumed to have the default net type, which is 'wire'. (VER-936)
Warning:  ./rtl/tpdn65lpnv2od3.v:262: the undeclared symbol 'PU' assumed to have the default net type, which is 'wire'. (VER-936)
Warning:  ./rtl/tpdn65lpnv2od3.v:263: the undeclared symbol 'PSB' assumed to have the default net type, which is 'wire'. (VER-936)
Warning:  ./rtl/tpdn65lpnv2od3.v:264: the undeclared symbol 'PD' assumed to have the default net type, which is 'wire'. (VER-936)
Warning:  ./rtl/tpdn65lpnv2od3.v:265: the undeclared symbol 'PAD_q' assumed to have the default net type, which is 'wire'. (VER-936)
Warning:  ./rtl/tpdn65lpnv2od3.v:266: the undeclared symbol 'DS_tmp' assumed to have the default net type, which is 'wire'. (VER-936)
Error:  ./rtl/tpdn65lpnv2od3.v:273: case equality (===) is not supported by synthesis. (VER-189)
Warning:  ./rtl/tpdn65lpnv2od3.v:273: The construct '$test$plusargs system function' is not supported in synthesis; it is ignored. (VER-708)
Error:  ./rtl/tpdn65lpnv2od3.v:275: case equality (===) is not supported by synthesis. (VER-189)
Error:  Too many errors; can't continue. (VER-40)
*** Presto compilation terminated with 21 errors. ***
Running PRESTO HDLC
Error:  ./rtl/binmp.v:33: Type query about dimensions or access by indexing requires an array reference as the first argument. (ELAB-400)
*** Presto compilation terminated with 1 errors. ***
Error: Current design is not defined. (UID-4)
Error: Current design is not defined. (UID-4)
Error: Current design is not defined. (UID-4)
Error: Can't find object 'pad_Clk'. (UID-109)
Error: Value for list 'source_objects' must have 1 elements. (CMD-036)
Error: Current design is not defined. (UID-4)
Error: Can't find object 'pad_Clk'. (UID-109)
Error: Value for list 'object_list' must have 1 elements. (CMD-036)
Error: Current design is not defined. (UID-4)
Error: Can't find clock 'pad_Clk'. (UID-109)
Error: Value for list 'object_list' must have 1 elements. (CMD-036)
Error: Current design is not defined. (UID-4)
Error: Can't find clock 'pad_Clk'. (UID-109)
Error: Value for list 'object_list' must have 1 elements. (CMD-036)
Error: Current design is not defined. (UID-4)
Error: Can't find clock 'pad_Clk'. (UID-109)
Error: Value for list 'clock_list' must have 1 elements. (CMD-036)
Error: Current design is not defined. (UID-4)
Error: Can't find ports matching '*'. (UID-109)
Error: Value for list 'objects' must have 1 elements. (CMD-036)
Error: Current design is not defined. (UID-4)
Error: Current design is not defined. (UID-4)
Error: Can't find clock 'pad_Clk'. (UID-109)
Error: Value for list '-clock' must have 1 elements. (CMD-036)
Error: Value for list 'port_pin_list' must have 1 elements. (CMD-036)
Error: Current design is not defined. (UID-4)
Error: Current design is not defined. (UID-4)
Error: Can't find clock 'pad_Clk'. (UID-109)
Error: Value for list '-clock' must have 1 elements. (CMD-036)
Error: Value for list 'port_pin_list' must have 1 elements. (CMD-036)
Error: Current design is not defined. (UID-4)
Error: Current design is not defined. (UID-4)
Error: Can't find object 'clk_iopad'. (UID-109)
Error: Current design is not defined. (UID-4)
Error: Can't find object 'Rst_n_iopad'. (UID-109)
Error: Current design is not defined. (UID-4)
Error: Can't find object 'hidden_in_iopad0'. (UID-109)
Error: Current design is not defined. (UID-4)
Error: Can't find object 'hidden_in_iopad1'. (UID-109)
Error: Current design is not defined. (UID-4)
Error: Can't find object 'hidden_in_iopad2'. (UID-109)
Error: Current design is not defined. (UID-4)
Error: Can't find object 'hidden_in_iopad3'. (UID-109)
Error: Current design is not defined. (UID-4)
Error: Can't find object 'W2_iopad0'. (UID-109)
Error: Current design is not defined. (UID-4)
Error: Can't find object 'W2_iopad1'. (UID-109)
Error: Current design is not defined. (UID-4)
Error: Can't find object 'W2_iopad2'. (UID-109)
Error: Current design is not defined. (UID-4)
Error: Can't find object 'W2_iopad3'. (UID-109)
Error: Current design is not defined. (UID-4)
Error: Can't find object 'W2_iopad4'. (UID-109)
Error: Current design is not defined. (UID-4)
Error: Can't find object 'W2_iopad5'. (UID-109)
Error: Current design is not defined. (UID-4)
Error: Can't find object 'en_iopad'. (UID-109)
Error: Current design is not defined. (UID-4)
Error: Can't find object 'out_iopad0'. (UID-109)
Error: Current design is not defined. (UID-4)
Error: Can't find object 'out_iopad1'. (UID-109)
Error: Current design is not defined. (UID-4)
Error: Can't find object 'out_iopad2'. (UID-109)
Error: Current design is not defined. (UID-4)
Error: Can't find object 'out_iopad3'. (UID-109)
Error: Current design is not defined. (UID-4)
Error: Can't find object 'out_iopad4'. (UID-109)
Error: Current design is not defined. (UID-4)
Error: Can't find object 'out_iopad5'. (UID-109)
Error: Current design is not defined. (UID-4)
Error: Can't find object 'out_iopad6'. (UID-109)
Error: Current design is not defined. (UID-4)
Error: Can't find object 'out_iopad7'. (UID-109)
Error: Current design is not defined. (UID-4)
Error: Can't find object 'out_iopad8'. (UID-109)
Error: Current design is not defined. (UID-4)
Error: Can't find object 'out_iopad9'. (UID-109)
Error: Value for list 'object_list' must have 1 elements. (CMD-036)
Information: Auto ungrouping of the design is disabled because the '-no_boundary_optimization' is used. (OPT-1316)
Warning: The value of variable 'compile_preserve_subdesign_interfaces' has been changed to true because '-no_boundary_optimization' is used. (OPT-133)
Information: Starting from 2013.12 release, constant propagation is enabled even when boundary optimization is disabled. (OPT-1318)
Error: Current design is not defined. (UID-4)
Error: Current design is not defined. (UID-4)
Error: Current design is not defined. (UID-4)
Error: Current design is not defined. (UID-4)

coolbear2021

ahzhangyq 发表于 2022-1-4 17:04
你好，能帮我看一下吗？ 照着写的，还是有问题。
代码文件为：

应该是综合设置的问题。io的.v文件不要加到综合的rtl里，那个.v是不可综合的。
io是以lib的方式使用的，要把io的db文件加到link_library里去。

ahzhangyq

coolbear2021 发表于 2022-1-5 08:45
应该是综合设置的问题。io的.v文件不要加到综合的rtl里，那个.v是不可综合的。
io是以lib的方式使用的， ...

io.db已经加进去了，不加io.v还是有问题，还把例化单元设置成了dont_touch.
问题如下：
Error:  ./rtl/binmp.v:26: Type query about dimensions or access by indexing requires an array reference as the first argument. (ELAB-400)
*** Presto compilation terminated with 1 errors. ***

Error: Current design is not defined. (UID-4)
Error: Current design is not defined. (UID-4)
Error: Current design is not defined. (UID-4)
Error: Can't find object 'Clk'. (UID-109)
Error: Value for list 'source_objects' must have 1 elements. (CMD-036)
Error: Current design is not defined. (UID-4)
Error: Can't find object 'Clk'. (UID-109)
Error: Value for list 'object_list' must have 1 elements. (CMD-036)
Error: Current design is not defined. (UID-4)
Error: Can't find clock 'Clk'. (UID-109)
Error: Value for list 'object_list' must have 1 elements. (CMD-036)
Error: Current design is not defined. (UID-4)
Error: Can't find clock 'Clk'. (UID-109)
Error: Value for list 'object_list' must have 1 elements. (CMD-036)
Error: Current design is not defined. (UID-4)
Error: Can't find clock 'Clk'. (UID-109)
Error: Value for list 'clock_list' must have 1 elements. (CMD-036)
Error: Current design is not defined. (UID-4)
Error: Can't find ports matching '*'. (UID-109)
Error: Value for list 'objects' must have 1 elements. (CMD-036)
Error: Current design is not defined. (UID-4)
Error: Current design is not defined. (UID-4)
Error: Can't find clock 'Clk'. (UID-109)
Error: Value for list '-clock' must have 1 elements. (CMD-036)
Error: Value for list 'port_pin_list' must have 1 elements. (CMD-036)
Error: Current design is not defined. (UID-4)
Error: Current design is not defined. (UID-4)
Error: Can't find clock 'Clk'. (UID-109)
Error: Value for list '-clock' must have 1 elements. (CMD-036)
Error: Value for list 'port_pin_list' must have 1 elements. (CMD-036)
Error: Current design is not defined. (UID-4)
Error: Current design is not defined. (UID-4)
Error: Can't find object 'clk_iopad'. (UID-109)
Error: Current design is not defined. (UID-4)
Error: Can't find object 'Rst_n_iopad'. (UID-109)
Error: Current design is not defined. (UID-4)
Error: Can't find object 'hidden_in_iopad0'. (UID-109)
Error: Current design is not defined. (UID-4)
Error: Can't find object 'hidden_in_iopad1'. (UID-109)
Error: Current design is not defined. (UID-4)
Error: Can't find object 'hidden_in_iopad2'. (UID-109)
Error: Current design is not defined. (UID-4)
Error: Can't find object 'hidden_in_iopad3'. (UID-109)
Error: Current design is not defined. (UID-4)
Error: Can't find object 'W2_iopad0'. (UID-109)
Error: Current design is not defined. (UID-4)
Error: Can't find object 'W2_iopad1'. (UID-109)
Error: Current design is not defined. (UID-4)
Error: Can't find object 'W2_iopad2'. (UID-109)
Error: Current design is not defined. (UID-4)
Error: Can't find object 'W2_iopad3'. (UID-109)
Error: Current design is not defined. (UID-4)
Error: Can't find object 'W2_iopad4'. (UID-109)
Error: Current design is not defined. (UID-4)
Error: Can't find object 'W2_iopad5'. (UID-109)
Error: Current design is not defined. (UID-4)
Error: Can't find object 'en_iopad'. (UID-109)
Error: Current design is not defined. (UID-4)
Error: Can't find object 'out_iopad0'. (UID-109)
Error: Current design is not defined. (UID-4)
Error: Can't find object 'out_iopad1'. (UID-109)
Error: Current design is not defined. (UID-4)
Error: Can't find object 'out_iopad2'. (UID-109)
Error: Current design is not defined. (UID-4)
Error: Can't find object 'out_iopad3'. (UID-109)
Error: Current design is not defined. (UID-4)
Error: Can't find object 'out_iopad4'. (UID-109)
Error: Current design is not defined. (UID-4)
Error: Can't find object 'out_iopad5'. (UID-109)
Error: Current design is not defined. (UID-4)
Error: Can't find object 'out_iopad6'. (UID-109)
Error: Current design is not defined. (UID-4)
Error: Can't find object 'out_iopad7'. (UID-109)
Error: Current design is not defined. (UID-4)
Error: Can't find object 'out_iopad8'. (UID-109)
Error: Current design is not defined. (UID-4)
Error: Can't find object 'out_iopad9'. (UID-109)
Error: Value for list 'object_list' must have 1 elements. (CMD-036)
Information: Auto ungrouping of the design is disabled because the '-no_boundary_optimization' is used. (OPT-1316)
Warning: The value of variable 'compile_preserve_subdesign_interfaces' has been changed to true because '-no_boundary_optimization' is used. (OPT-133)
Information: Starting from 2013.12 release, constant propagation is enabled even when boundary optimization is disabled. (OPT-1318)
Error: Current design is not defined. (UID-4)
Error: Current design is not defined. (UID-4)
Error: Current design is not defined. (UID-4)
Error: Current design is not defined. (UID-4)

代码如下：
module binmp(
    input     wire    pad_Clk,
    input     wire    pad_Rst_n,
    input     wire    [3:0] pad_hidden_in,
    input     wire    [5:0] pad_W2,
    input     wire    pad_en,
    output  wire    [9:0] pad_out
);
Binary_Mult    u_Binary_Mult(
    .Clk(Clk),
    .Rst_n(Rst_n),
    .hidden_in(hidden_in),
    .W2(W2),
    .en(en),
    .out(out)
);

//iopad:    PDDW0204SCDG (I,DS,OEN,PAD,C,PE,IE);
//input:    (.I(1'b0),.DS(1'b0),.OEN(1'b1),.PAD(pad_),.C(),.PE(1'b0),.IE(1'b1));
//output:    (.I(),.DS(1'b1),.OEN(1'b0),.PAD(pad_),.C(),.PE(1'b1),.IE(1'b1));

// input
PDDW0204SCDG    clk_iopad             (.I(1'b0),.DS(1'b0),.OEN(1'b1),.PAD(pad_Clk),            .C(Clk),            .PE(1'b0),.IE(1'b1));
PDDW0204SCDG    Rst_n_iopad         (.I(1'b0),.DS(1'b0),.OEN(1'b1),.PAD(pad_Rst_n),            .C(Rst_n),            .PE(1'b0),.IE(1'b1));
PDDW0204SCDG    hidden_in_iopad0     (.I(1'b0),.DS(1'b0),.OEN(1'b1),.PAD(pad_hidden_in[0]),    .C(hidden_in[0]),    .PE(1'b0),.IE(1'b1));
PDDW0204SCDG    hidden_in_iopad1     (.I(1'b0),.DS(1'b0),.OEN(1'b1),.PAD(pad_hidden_in[1]),    .C(hidden_in[1]),    .PE(1'b0),.IE(1'b1));
PDDW0204SCDG    hidden_in_iopad2     (.I(1'b0),.DS(1'b0),.OEN(1'b1),.PAD(pad_hidden_in[2]),    .C(hidden_in[2]),    .PE(1'b0),.IE(1'b1));
PDDW0204SCDG    hidden_in_iopad3     (.I(1'b0),.DS(1'b0),.OEN(1'b1),.PAD(pad_hidden_in[3]),    .C(hidden_in[3]),    .PE(1'b0),.IE(1'b1));
PDDW0204SCDG    W2_iopad0             (.I(1'b0),.DS(1'b0),.OEN(1'b1),.PAD(pad_W2[0]),            .C(W2[0]),            .PE(1'b0),.IE(1'b1));
PDDW0204SCDG    W2_iopad1             (.I(1'b0),.DS(1'b0),.OEN(1'b1),.PAD(pad_W2[1]),            .C(W2[1]),            .PE(1'b0),.IE(1'b1));
PDDW0204SCDG    W2_iopad2             (.I(1'b0),.DS(1'b0),.OEN(1'b1),.PAD(pad_W2[2]),            .C(W2[2]),            .PE(1'b0),.IE(1'b1));
PDDW0204SCDG    W2_iopad3             (.I(1'b0),.DS(1'b0),.OEN(1'b1),.PAD(pad_W2[3]),            .C(W2[3]),            .PE(1'b0),.IE(1'b1));
PDDW0204SCDG    W2_iopad4             (.I(1'b0),.DS(1'b0),.OEN(1'b1),.PAD(pad_W2[4]),            .C(W2[4]),            .PE(1'b0),.IE(1'b1));
PDDW0204SCDG    W2_iopad5             (.I(1'b0),.DS(1'b0),.OEN(1'b1),.PAD(pad_W2[5]),            .C(W2[5]),            .PE(1'b0),.IE(1'b1));
PDDW0204SCDG    en_iopad              (.I(1'b0),.DS(1'b0),.OEN(1'b1),.PAD(pad_en),            .C(en),                .PE(1'b0),.IE(1'b1));
// output
PDDW0204SCDG    out_iopad0             (.I(out[0]),.DS(1'b1),.OEN(1'b0),.PAD(pad_out[0]),        .C(),                .PE(1'b0),.IE(1'b0));
PDDW0204SCDG    out_iopad1             (.I(out[1]),.DS(1'b1),.OEN(1'b0),.PAD(pad_out[1]),        .C(),                .PE(1'b0),.IE(1'b0));
PDDW0204SCDG    out_iopad2             (.I(out[2]),.DS(1'b1),.OEN(1'b0),.PAD(pad_out[2]),        .C(),                .PE(1'b0),.IE(1'b0));
PDDW0204SCDG    out_iopad3             (.I(out[3]),.DS(1'b1),.OEN(1'b0),.PAD(pad_out[3]),        .C(),                .PE(1'b0),.IE(1'b0));
PDDW0204SCDG    out_iopad4             (.I(out[4]),.DS(1'b1),.OEN(1'b0),.PAD(pad_out[4]),        .C(),                .PE(1'b0),.IE(1'b0));
PDDW0204SCDG    out_iopad5             (.I(out[5]),.DS(1'b1),.OEN(1'b0),.PAD(pad_out[5]),        .C(),                .PE(1'b0),.IE(1'b0));
PDDW0204SCDG    out_iopad6             (.I(out[6]),.DS(1'b1),.OEN(1'b0),.PAD(pad_out[6]),        .C(),                .PE(1'b0),.IE(1'b0));
PDDW0204SCDG    out_iopad7             (.I(out[7]),.DS(1'b1),.OEN(1'b0),.PAD(pad_out[7]),        .C(),                .PE(1'b0),.IE(1'b0));
PDDW0204SCDG    out_iopad8             (.I(out[8]),.DS(1'b1),.OEN(1'b0),.PAD(pad_out[8]),        .C(),                .PE(1'b0),.IE(1'b0));
PDDW0204SCDG    out_iopad9             (.I(out[9]),.DS(1'b1),.OEN(1'b0),.PAD(pad_out[9]),        .C(),                .PE(1'b0),.IE(1'b0));
endmodule

综合约束如下：
create_clock            -period    10    Clk
set_clock_latency        1.0    Clk
set_clock_uncertainty    -setup    0.5    [get_clocks    Clk]
set_clock_uncertainty    -hold    0.1    [get_clocks    Clk]
set_clock_transition    0.3    [get_clocks    Clk]
set_load                2    [get_ports    *]
set_input_delay            -clock    Clk    1.0    [all_inputs]
set_output_delay        -clock    Clk    0.5    [all_outputs]
set_operating_conditions    -max NCCOM

coolbear2021

ahzhangyq 发表于 2022-1-5 08:59
io.db已经加进去了，不加io.v还是有问题，还把例化单元设置成了dont_touch.
问题如下：
Error:  ./rtl/bi ...

已经没有io .v综合的错了，其它的错你要自己看看了，应该是这个错要解决的。
Error:  ./rtl/binmp.v:26: Type query about dimensions or access by indexing requires an array reference as the first argument. (ELAB-400)

ahzhangyq

coolbear2021 发表于 2022-1-5 09:27
已经没有io .v综合的错了，其它的错你要自己看看了，应该是这个错要解决的。
Error:  ./rtl/binmp.v:26:  ...

好的，多谢

郑伟

coolbear2021 发表于 2021-11-17 11:20
假定你的模块叫xxx，并且所有的port都要接到pad上，可以参考下面的代码。

你的代码里信号都是单向的，inpu ...

大神，我现在clk_main_in这个端口不需要例化到io_pad，那怎么在这个文件里例化一下接我本来文件的clk_main_in的端口呢

coolbear2021

郑伟 发表于 2022-2-24 10:14
大神，我现在clk_main_in这个端口不需要例化到io_pad，那怎么在这个文件里例化一下接我本来文件的clk_mai ...

可以把对应的io例化去掉，直接assign clk_main_in = pad_clk_main_in，就可以了。