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发表于 2020-11-16 15:29:49
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Title
Fixing Recovery and Removal Violations in Design Compiler
Description
Fixing Recovery and Removal Violations in Design Compiler
Question:
Does Design Compiler fix recovery and removal violations?
Answer:
If the enable_recovery_removal_arcs variable is set to true, Design Compiler
times and optimizes for timing checks along timing arc paths that end at an
asynchronous pin.
Design Compiler does not work on paths on which asynchronous timing arcs go
through sequential cells, such as the following:
input SET;
:
FD4 u0 (.D(din), .CP(clk), .SD(SET), .Q(regout1));
FD1 u1 (.D(regout1), .CP(clk), .Q(dout));
During synthesis, Design Compiler will not optimize the path from u0/SD -to u1/D,
because starting from the SET port and ending at u1/D, the path is not visible
to the tool.
Question:
Can you provide a simple example of recovery fixing?
Answer:
Recovery fixing is equivalent to setup time fixing, and removal
fixing is equivalent to hold time fixing. In Design Compiler, it
is essential to use set_fix_hold to fix the hold time.
Following is a small test case, which demonstrates how to use Design Compiler
to correct a recovery violation.
====== Commands to show the violation ============================
set target_library lsi_10k.db
set link_library "* $target_library"
set enable_recovery_removal_arcs true
read_ver simple.v
create_clock -p 10 CLK
set_input_delay 9 -clock CLK RESET
report_timing
compile -inc
report_timing
====== test module simple.v ======================================
module simple (CLK, A, RESET, Z);
input CLK, A, RESET;
output Z;
IV U1 (.A(RESET), .Z(RESET_BAR));
FD2 REG (.CP(CLK), .CD(RESET_BAR), .D(A), .Q(Z));
endmodule
====== Commands to fix the violation =============================
set target_library lsi_10k.db
set link_library "* $target_library"
set enable_recovery_removal_arcs true
read_ver simple.v
create_clock -p 10 CLK
set_input_delay 9 -clock CLK RESET
report_timing
set_fix_hold CLK
compile -inc
report_timing
Question:
Can you recommend some related SolvNet articles?
Answer:
See the following articles for more information on recovery and removal timing:
SolvNet article 901257, "How to Check Recovery and Removal Timing for Asynchronous set/reset Signals"
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