关于Techgen转QRC文件的流程

Hric · 发表于 2023-11-1 16:55:58

学习一下

猫哥 · 发表于 2023-12-4 06:41:14

上面的warnning 解决了但是还是报ERROR 这个是咋回事呢

小李飞刀 · 发表于 2024-4-24 10:05:53

猫哥发表于 2023-12-4 06:41
上面的warnning 解决了但是还是报ERROR 这个是咋回事呢

老哥你解决这个问题了吗？我也遇到了一样的问题，可以说一下该怎么解决吗？

攀登者 · 发表于 2024-5-24 13:57:01

axxqql 发表于 2019-12-27 11:16
这个东西转的就是很慢的。晚上丢下去。 -multi_cpu 不怕被骂你就写8啊,16啊。。。

请问怎么调呢？直接改ict的内容吗、还是改脚本？

hevendai · 发表于 2024-6-19 22:50:22

我来解答吧,很简单,就是高度累加误差导致的.
我也折腾了好久,终于解决了!!!!
要手动改:看懂下面我例子就ok了.
40.01 itf to icl
./itf_to_ict.pl  ./StarRC_40LL_1P9M_2TM_CMAX.itf ./StarRC_40LL_1P9M_2TM_CMAX.ict

40.02 icl to qrc
Techgen  -simulation -multi_cpu 8  ./StarRC_40LL_1P9M_2TM_CMAX.ict
如果报ERROR (EXTZTECH-213) : Error [input]: Layers ppoly and npoly in ICT file overlap.
都是高度累加value有问题，一定能要手动修改height值：
如果是poly要定义subconductor （因为不能设置厚度为0或者小于0的值，只有sub_conductor才有相同的height）
正确为：
conductor poly {
min_spacing          5.7600E-02
min_contact_poly_spacing 0.036
min_width          3.6000E-02
height             3.5000E-01
thickness          7.7000E-02
resistivity          1.6000E+01
temp_tc1             1.6600E-03
temp_tc2             -2.9500E-07
gate_forming_layer true
layer_type gate
sub_conductor npoly {
height             3.5000E-01
thickness          7.7000E-02
resistivity          1.6000E+01
temp_tc1             1.6600E-03
temp_tc2             -2.9500E-07
wire_edge_enlargement_c {
   wee_widths  3.6000E-02
   wee_spacings 5.7600E-02
   wee_adjustments 0.0025
  }
wire_edge_enlargement_r {
   wee_widths  3.6000E-02
   wee_spacings 5.7600E-02
   wee_adjustments -0.0
  }
}
sub_conductor ppoly {
height             3.5000E-01
thickness          7.7000E-02
resistivity          1.2820E+01
temp_tc1             1.9200E-03
temp_tc2             -3.4000E-07
wire_edge_enlargement_c {
   wee_widths  3.6000E-02
   wee_spacings 5.7600E-02
   wee_adjustments 0.0025
  }
wire_edge_enlargement_r {
   wee_widths  3.6000E-02
   wee_spacings 5.7600E-02
   wee_adjustments 0.00376
  }
}
}
错误为：
#conductor ppoly {
# min_spacing       5.7600E-02
# min_width    3.6000E-02
# height       0.352565
# thickness    7.7000E-02
# resistivity
# temp_tc1         1.9200E-03
# temp_tc2         -3.4000E-07
# gate_forming_layer       true
# wire_edge_enlargement_c {
#    wee_widths  3.6000E-02
#    wee_spacings 5.7600E-02
#    wee_adjustments       0.0025
#  }
#}

#conductor npoly {
# min_spacing       5.7600E-02
# min_width    3.6000E-02
# height       0.352565
# thickness    7.7000E-02
# resistivity       1.6000E+01
# temp_tc1         1.6600E-03
# temp_tc2         -2.9500E-07
# gate_forming_layer       false
# wire_edge_enlargement_c {
#    wee_widths  3.6000E-02
#    wee_spacings 5.7600E-02
#    wee_adjustments       0.0025
#  }
#}
另外也有报
ERROR (EXTZTECH-206) : Error [input]: Layers ILD1a and ILD1b1 are not touching.
因为下面：
dielectric ILD1a {
conformal    TRUE
expandedFrom    poly
height    0.3525
thickness    0.0380  ( -> changed to 0.0381 to pass check!!!)
topThickness    0.0380
sideExpand    0.0304
dielectric_constant    7.000
}

dielectric ILD1b1 {
conformal    FALSE
height    0.3906 != 0.3525+0.0380=0.3905
thickness    0.1420
dielectric_constant    4.200
}
如上将高度height改成一样就可以，通常是改thickness，例如将ILD1a 的thickness    0.0380-> changed to 0.0381
都是因为厚度thickness精度误差导致的。

hevendai · 发表于 2024-6-19 22:51:20

我来解答吧,很简单,就是高度累加误差导致的.
我也折腾了好久,终于解决了!!!!
要手动改:看懂下面我例子就ok了.
40.01 itf to icl
./itf_to_ict.pl  ./StarRC_40LL_1P9M_2TM_CMAX.itf ./StarRC_40LL_1P9M_2TM_CMAX.ict

40.02 icl to qrc
Techgen  -simulation -multi_cpu 8  ./StarRC_40LL_1P9M_2TM_CMAX.ict
如果报ERROR (EXTZTECH-213) : Error [input]: Layers ppoly and npoly in ICT file overlap.
都是高度累加value有问题，一定能要手动修改height值：
如果是poly要定义subconductor （因为不能设置厚度为0或者小于0的值，只有sub_conductor才有相同的height）
正确为：
conductor poly {
min_spacing          5.7600E-02
min_contact_poly_spacing 0.036
min_width          3.6000E-02
height             3.5000E-01
thickness          7.7000E-02
resistivity          1.6000E+01
temp_tc1             1.6600E-03
temp_tc2             -2.9500E-07
gate_forming_layer true
layer_type gate
sub_conductor npoly {
height             3.5000E-01
thickness          7.7000E-02
resistivity          1.6000E+01
temp_tc1             1.6600E-03
temp_tc2             -2.9500E-07
wire_edge_enlargement_c {
   wee_widths  3.6000E-02
   wee_spacings 5.7600E-02
   wee_adjustments 0.0025
  }
wire_edge_enlargement_r {
   wee_widths  3.6000E-02
   wee_spacings 5.7600E-02
   wee_adjustments -0.0
  }
}
sub_conductor ppoly {
height             3.5000E-01
thickness          7.7000E-02
resistivity          1.2820E+01
temp_tc1             1.9200E-03
temp_tc2             -3.4000E-07
wire_edge_enlargement_c {
   wee_widths  3.6000E-02
   wee_spacings 5.7600E-02
   wee_adjustments 0.0025
  }
wire_edge_enlargement_r {
   wee_widths  3.6000E-02
   wee_spacings 5.7600E-02
   wee_adjustments 0.00376
  }
}
}
错误为：
#conductor ppoly {
# min_spacing       5.7600E-02
# min_width    3.6000E-02
# height       0.352565
# thickness    7.7000E-02
# resistivity
# temp_tc1         1.9200E-03
# temp_tc2         -3.4000E-07
# gate_forming_layer       true
# wire_edge_enlargement_c {
#    wee_widths  3.6000E-02
#    wee_spacings 5.7600E-02
#    wee_adjustments       0.0025
#  }
#}

#conductor npoly {
# min_spacing       5.7600E-02
# min_width    3.6000E-02
# height       0.352565
# thickness    7.7000E-02
# resistivity       1.6000E+01
# temp_tc1         1.6600E-03
# temp_tc2         -2.9500E-07
# gate_forming_layer       false
# wire_edge_enlargement_c {
#    wee_widths  3.6000E-02
#    wee_spacings 5.7600E-02
#    wee_adjustments       0.0025
#  }
#}
另外也有报
ERROR (EXTZTECH-206) : Error [input]: Layers ILD1a and ILD1b1 are not touching.
因为下面：
dielectric ILD1a {
conformal    TRUE
expandedFrom    poly
height    0.3525
thickness    0.0380  ( -> changed to 0.0381 to pass check!!!)
topThickness    0.0380
sideExpand    0.0304
dielectric_constant    7.000
}

dielectric ILD1b1 {
conformal    FALSE
height    0.3906 != 0.3525+0.0380=0.3905
thickness    0.1420
dielectric_constant    4.200
}
如上将高度height改成一样就可以，通常是改thickness，例如将ILD1a 的thickness    0.0380-> changed to 0.0381
都是因为厚度thickness精度误差导致的。

向天笑白羊 · 发表于 2024-7-2 14:38:34

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