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楼主: wuyingpan06

systemverilog 和systemc,e,evra语言比较,有哪些优缺点?questa与vcs有哪些优缺点?

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发表于 2008-3-22 22:34:48 | 显示全部楼层

怎么都是不了解都下结论

请问说modelsim不行的你知道intel用的就是modelsim吗?说e不行的那位你知道e在很多方面优于systemverilog。在国外specman的应用也非常的广泛。所以我想大家在下结论时,最好先确认一下自己说的是否真的对。
发表于 2008-3-25 21:10:21 | 显示全部楼层
看好systemverilog
发表于 2008-3-26 14:33:14 | 显示全部楼层

ic猎头急招Senior FPGA/Verification Engineer待遇不错的

目前我客户(知名ic企业)在招以上人才,待遇不错如果需要请联系我,如果方面把您的最新简历发给我一份谢谢!
联系方式:021-62828153         
msn:zyqic@hotmail.com         mail: terry@chinaeejob.com
具体描述
Job Responsibilities:
Reporting to Verification manager, the candidate is expected to be responsible for following tasks:
-Apply specialist skills and knowledge in both hardware and software to perform Pre-Silicon verification tasks for Media Processor SOC devices
-Perform co-verification of processor models and RTL including application software and firmware verification
-Support the development of multi abstraction/views to enable a thorough Soc verification from unit level to system level
-Participation in the continued development of verification strategies; evaluate and integrate cutting edge verification methodologies into the tool flow
-Work with other cross functional teams in China and oversea to specify, verify and improve SoC quality and timeliness to production

Job Requirements:
-Bachelor degree in Electrical Engineering or related area, MSEE is preferred.
-3 years or above experience in ASIC/complex SoC design or verification.
-Experience of SOC designs with embedded processor cores and their integration with other system components including memory subsystems and peripherals.
-Familiar with Microprocessor and/or DSP instruction sets and how low level driver software integrates into SOC architecture.
-Familiar with HDL languages, simulation tools and testbench design, low level assembler languages and C, or C++, scripting languages
头像被屏蔽
发表于 2008-4-26 11:28:02 | 显示全部楼层
提示: 作者被禁止或删除 内容自动屏蔽
发表于 2008-10-13 16:30:17 | 显示全部楼层
goodgood
发表于 2009-1-9 11:36:47 | 显示全部楼层
也来学习 等高人给意见
发表于 2009-1-31 17:37:07 | 显示全部楼层
看好SystemC!
发表于 2009-2-4 00:58:23 | 显示全部楼层
没有具体用过 只是感觉每种语言应该在其特定的方向能体现出一定的优势
发表于 2009-2-6 22:31:39 | 显示全部楼层
system verilog是从vera发展来的吧
发表于 2009-2-6 22:33:06 | 显示全部楼层
vcs是个环境而已吧
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