柯明道－ESD failure of analog IO cells in 0.18um CMOS

semico_ljj

論文名稱	ESD failure mechanisms of analog I/O cells in a 0.18-um CMOS technology

期刊	Ming-Dou Ker, S.-H. Chen, and C.-H. Chuang “ESD failure mechanisms of analog I/O cells in a 0.18-um CMOS technology,” IEEE Trans. on Device and Materials Reliability, vol. 6, no. 1, pp. 102-111, Mar. 2006.
摘要	Different electrostatic discharge (ESD) protection schemes have been investigated to find the optimal ESD protection design for an analog input/output (I/O) buffer in 0.18-um 1.8- and 3.3-V CMOS technology. Three power-rail ESD clamp devices were used in power-rail ESD clamp circuits to compare the protection efficiency in analog I/O applications, namely: 1) gate-driven NMOS; 2) substrate-triggered field-oxide device, and 3) substrate-triggered NMOS with dummy gate. From the experimental results, the pure-diode ESD protection devices and the power-rail ESD clamp circuit with gate-driven NMOS are the suitable designs for the analog I/O buffer in the 0.18-um CMOS process. Each ESD failure mechanism was inspected by scanning electron microscopy photograph in all the analog I/O pins. An unexpected failure mechanism was found in the analog I/O pins with pure-diode ESD protection design under ND-mode ESD stress. The parasitic n-p-n bipolar transistor between the ESD clamp device and the guard ring structure was trggered to discharge the ESD current and cause damage under ND-mode ESD stress.
關鍵字	Analog I/O, electrostatic discharge (ESD), failure mechanism, input/output (I/O) cell, power-rail ESD clamp device

eleven7up

很棒的論文
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gie_kong

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semico_ljj

sting_lover

很棒的論文

sting_lover

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haicoal

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averyer

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blinder

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