招聘验证工程师

Cissy_pq

Common:
1)
Familiar with system Verilog and UVM methodology
2)
Familiar with UNIX/Linux shell
3)
Familiar with Perl script
4)
Provide test plan basing on the design spec
5)
Setup the module level and chip level DV environment
6)
RTL simulation and netlist with timing simulation
7)
Implement the test cases basing test plan, and provide the test coverage
8)
Work with design team to repeat the failure case and find out root cause

Position 1:
1)
Familiar with the PCIe and NVMe protocol
2)
Familiar with SATA protocol
3)
Familiar with the NAND behavior and ONFI protocol
4)
Knowledge on ARM9 CPU core and AHB bus
5)
Knowledge on DDR3/LPDDR2
6)
Knowledge on AES and BCH ECC will be a plus

Position 2:
1)
Familiar with eMMC protocol
2)
Familiar with the NAND behavior and ONFI protocol
3)
Knowledge on BCH ECC

Postion 3:
1)    Familar with mixed signal design and/or verification

Postion 4:
1)  Familar with one of the areas below:
     a. ARM A9 subsystem
     b. DDR3/DDR4
     c. USB 3.0
     d. SATA
     e. PCIe
     f. Ethernet
（在上海或者北京工作）send resume to cissy_pq@163.com if you are interested.