timing violations after ICC route

xiaoyisimonguo

I read the timing violation report after route in ICC
there are a few lines: I could not understand, please help
-------------report-----------------
clock network delay (propagated)                        1.05       1.05
  I_ORCA_TOP/I_PCI_CORE/d_out_p_bus_reg_4_/CP (dfcrq4)
                                                          0.00       1.05 r
  I_ORCA_TOP/I_PCI_CORE/d_out_p_bus_reg_4_/Q (dfcrq4)    12.86 @    13.91 f
  I_ORCA_TOP/I_PCI_CORE/pframe_n_out (PCI_CORE_pci_data_width16)
                                                          0.00      13.91
--------------------------------------

Q1: where is 12.86, above in red, coming from?
Q2: a simple DFF, dfcrq4 in this case, clock 2 Q would never be 12.86ns, I did check the wire connect to Q
only 120u at the most, and CP wire is only 500u at most
Q3: sdc did not define pin loading though, could that be the reason?

Please help

xiaoyisimonguo

回复 1# xiaoyisimonguo


   need an expert for those questions

hjacky2010

可以开report_timing -verbose 看一下transition value是不是正常，正常情况下tool不该查出这么大的clk2q delay

kevin_zlm

可以查看下这个cell的fanout。

xworld2008

all_connect看连接了多少个cell

xiaoyisimonguo

回复 4# kevin_zlm


   Thank you kevin_zlm, for the reply
I don't know how to find out the fanout of the cell instance:

I_ORCA_TOP/I_PCI_CORE/d_out_p_bus_reg_4_

but from the layout I could tell it is only one-to-one to the pin, pframe_n, the wire is only about 120u
and the cell, dfcrq4, should be good enough

xiaoyisimonguo

回复 3# hjacky2010

thank you, hjacky2010, for replying
how do we check the transition time, report_timing -verbose did not work,

kevin_zlm

fanout and transition time ：report_timing -to * -derate -transition_time

xiaoyisimonguo

回复 8# kevin_zlm


    Thank you, kevin_zlm, that worked:
Point                                       Fanout     Trans    Derate      Incr       Path
  ----------------------------------------------------------------------------------------------
  clock PCI_CLK (rise edge)                                                   0.00       0.00
  clock network delay (propagated)                                            1.05       1.05
  I_ORCA_TOP/I_PCI_CORE/d_out_p_bus_reg_4_/CP (dfcrq4)
                                                          0.29                0.00       1.05 r
  I_ORCA_TOP/I_PCI_CORE/d_out_p_bus_reg_4_/Q (dfcrq4)    30.68               12.86 @    13.91 f
  I_ORCA_TOP/I_PCI_CORE/pframe_n_out (net)      1                             0.00      13.91 f
  I_ORCA_TOP/I_PCI_CORE/pframe_n_out (PCI_CORE_pci_data_width16)              0.00      13.91 f
-------------------------------------------------------------------------------------------------
but why trans reported 30.68, where did it come from?

kevin_zlm

回复 9# xiaoyisimonguo


    report_delay_calculation