timing violations after ICC route

intern7

thanks

分特

report_timing -cap -net -trans

xiaoyisimonguo

回复 10# kevin_zlm
Thank you, kevin_zlm, for your replyIt is quite a surprise, ICC placement and route procedures should see the same information, Why didn't placement or route insert a buffer between Q and pin pframe_n to avoid DFF Q directly drive that 15pF?
Please help


report_delay_calculation -from  I_ORCA_TOP/I_PCI_CORE/d_out_p_bus_reg_4_/CP -to I_ORCA_TOP/I_PCI_CORE/d_out_p_bus_reg_4_/Q
report:
---------------------------
Arnoldi-based Delay Calculation:
   RC network on pin 'I_ORCA_TOP/I_PCI_CORE/d_out_p_bus_reg_4_/Q' :
   ------------------------------------------------------
   Number of elements = 8 Capacitances + 7 Resistances
   Total capacitance  = 15.014811 pF
   Total capacitance  = 15.014811 (in main library unit)
   Total resistance   = 0.078812 Kohm

                              Rise        Fall
   ------------------------------------------------------------------
   Input transition time  = 0.286831    0.293038  (in main library unit)
   Effective capacitance  = 13.729464    14.193019  (in pF)
   Effective capacitance  = 13.729464    14.193019  (in main library unit)
   Drive resistance       = 0.650681    0.647745  (in Kohm)
   Output transition time = 26.554968    30.681604  (in main library unit)
   Cell delay             = 9.914715    12.855111  (in main library unit)