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哪位大虾有以下paper的详细资料，
请不吝共享。
ISSCC2006 Session 12
12.3 A 30mW 12b 40MS/s Subranging ADC with a High-Gain Offset-Canceling Positive-Feedback Amplifier in 90nm Digital CMOS 9:30 AM
Y. Shimizu, S. Murayama, K. Kudoh, H. Yatsuda, A. OgawaSony, Nagasaki, Japan
A 12b 40MS/s 2-step subranging ADC is realized in a 90nm digital CMOS process.
It uses a 7b coarse quantizer with a high-gain offset-canceling positive-feedback
amplifier. ENOB is 10.2b at a 0.7V supply and 11.0b at a 1.0V supply. The ADC
consumes 30mW at 40MS/s. |
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发表于 2007-5-31 08:23:28