做Dig-PLL,求下载论文，谢谢！

mainhand

[28] H. S. Kim et al., “A digital fractional-N PLL with a PVT and mismatch insensitive TDC utilizing equivalent time sampling technique,” IEEE J.Solid-State Circuits, vol. 48, no. 7, p. 1721, Jul. 2013.

[29] S.-J. Kim, W. Kim, M. Song, J. Kim, T. Kim, and H. Park, “A 0.6V 1.17 ps PVT-tolerant and synthesizable time-to-digital converter using stochastic phase interpolation with 16x spatial redundancy in 14 nm FinFET technology,” in IEEE Int. Solid-State Circuits Conf. Dig. Tech.Papers, Feb. 2015, pp. 280–281.

[30] J. Borremans, K. Vengattaramane, V. Giannini, B. Debaillie, W. VanThillo, and J. Craninckx, “A 86 MHz–12 GHz digital-intensive PLL for software-defined radios, using a 6 fJ/Step TDC in 40 nm digital CMOS,”IEEE J. Solid-State Circuits, vol. 45, no. 10, p. 2116, Oct. 2010.

[31] J.-P. Hong et al., “A 0.004mm2 250 μW ΔΣ TDC with time-difference accumulator and a 0.012mm2 2.5 mW bang-bang digital PLL using PRNG for low-power SoC applications,” in IEEE Int. Solid-State Circuits Conf. Dig. Tech. Papers, Feb. 2012, pp. 240–241.

mainhand

自己顶一个！

lipinshengxp

非常好的书！！！

alhoceima111

thanks