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Hi All,
这边是Synopsys HR, Aria, 我们在武汉的研发中心招聘一名design manager, 具体职位描述如下,有意向的朋友,欢迎发送简历到 Qianyi.Zhong@synopsys.com, 另外,上海/北京/深圳也均有前端后端相关职位,更多职位欢迎邮件咨询。
收到简历后,我们会尽快与你联系,谢谢!
Job Title: mgr, ASIC digital design
Location: Wuhan
Job Description:
Seeking a highly motivated, organized, and technically strong candidate for the role of a ASIC Digital Design Manager, who can lead the digital development and maintenance of the SERDES IP portfolio, including, USB2.0, HSIC, OTG, USB3.1, PCIe1/2/3/4, SATA 1/2/3, KX/KX4/KR. The position offers a great opportunity to work with highly experienced teams of digital, analog, and system designers, who have been responsible for developing the next generation of SERDES IP for various interface protocols.
Job Responsibilities:
Manage the local and off-site digital design and verification teams responsible for SERDES hard and soft RTL IP development.
Interface with the Application Engineering team, Digital Place and Route team, Analog design team, and Technical Marketing team.
Act as a technical lead for the design projects. Review the standards specifications, prepare architecture specifications, provide guidelines and review RTL implementation, synthesis constraints, ATPG, and ATE vector generation.
Conduct performance reviews of the team members and provide constructive and accurate feedback to the team members.
Job Requirements:
BS with 10 years, or MS with 6 years of digital design and verification experience in the industry. In addition, at least 1 year of experience as a technical manager or a technical lead in ASIC development team.
Must have deep understanding of asynchronous clock crossings, UPF based power-gating, DFT design methodologies, and synthesis implications of RTL. Knowledge of back-end synthesis tools DC/PT is a plus.
Good organization and communication skills for interacting between different design groups and customer support teams across sites.
Knowledge of Interface standards is a plus. |
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