fix timing的方法大概有以下几种:1. size_cell
2. userful skew
3. insert_buffer
4. move cell location.
5. logic remap, like change the buffer to two inverter cells, this is quite similar like 3, which both try to cut the long net into smaller piece or split the sink.
6. You might also want to use some clone cell skills.
The most import is you need to know you have have these violations, then choose correponding solution to fix the violation.