Improve ESD Robustness in 130nm (Ming-Dou Ker)

semico_ljj

Dummy-Gate Structure to Improve ESD Robustness in a Fully-Salicided
130-nm CMOS Technology without Using Extra Salicide-Blocking Mask

Hsin-Chyh Hsu and Ming-Dou Ker
Nanoelectronics and Gigascale Systems Lab.
Institute of Electronics, National Chiao-Tung University, Taiwan
E-mail: HCHsu@ieee.org

Abstract
NMOS with dummy-gate structure is proposed to
significantly improve electrostatic discharge (ESD)
robustness in a fully-salicided CMOS technology. By using
this structure, ESD current is discharged far away from
the salicided surface channel of NMOS, therefore the
NMOS can sustain a much higher ESD level. The HBM
(MM) ESD robustness of the NMOS with dummy-gate
structure (W/L = 480 μm/0.18 μm) has been successfully
improved from 0.5 kV (125 V) to 1.5 kV (325 V) in a
130-nm fully-salicided CMOS process. Under the same
layout area of the gate-grounded NMOS (ggNMOS), HBM
(MM) ESD level can be improved over 300% (260%) by
the proposed dummy-gate structure. The proposed
dummy-gate structure is fully process compatible to
general salicided CMOS processes without additional
mask, which is very cost-efficient for application in the IC
products.

arsin

thank you

sjxu007

good stuff

sud6

谢谢分享