Vivado的debug core怎么用？

linghuqiubai

按网上查的方法来，在最后烧bit文件时总是报下面的warning：

1. WARNING: [Xicom 50-38] xicom: No CseXsdb register file specified for CseXsdb slave type: 0, cse driver version: 0. Slave initialization skipped.
   
2. INFO: [Labtools 27-1434] Device xc7k410t (JTAG device index = 0) is programmed with a design that has no supported debug core(s) in it.
   
3. WARNING: [Labtools 27-3123] The debug hub core was not detected at User Scan Chain 1 or 3. You must manually launch hw_server
   
4. with -e "set xsdb-user-bscan <C_USER_SCAN_CHAIN scan_chain_number>" to detect the debug hub at User Scan Chain of 2 or 4.
   
5. To determine the user scan chain setting, open the implemented design and use: get_property C_USER_SCAN_CHAIN [get_debug_cores dbg_hub].
   
6. WARNING: [Labtools 27-1974] Mismatch between the design programmed into the device xc7k410t_0 and the probes file D:/Vivado/xc7k410t-2ffg900/ddr_slave_410t_20150527_1/ddr_slave_410t_20150527_1.runs/impl_1/debug_nets.ltx.
   
7. The device design has 0 ILA core(s) and 0 VIO core(s). The probes file has 1 ILA core(s) and 0 VIO core(s).
   
8. Resolution:
   
9. 1. Reprogram device with the correct programming file and associated probes file OR
   
10. 2. Goto device properties and associate the correct probes file with the programming file already programmed in the device.
    
11. 
    

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大概是说设计里没有ILA core，但是debug文件里有ILA core，而且debug probes窗口下什么也没有。但是，我综合后明明插入了debug core呀，而且在约束文件里也自动生成了相关信息，查看schematic，也添加了debug相关的两个元件，为毛program时就是看不到呢？
不知道有没有人遇到过类似的情况，求指点，万分感谢！

wilfred

VIO 和 ILA 的CLK 有问题。

xduryan

1，重新生成下看看，IPcore版本不对

linghuqiubai

回复 2# xduryan


   试过好几次都不行，版本不对是啥意思？

greenpine

确认一下probe文件

linghuqiubai

回复 4# greenpine


   没什么问题呀

linghuqiubai

回复 6# wilfred

我查的Xilinx的论坛，貌似也这么说，说是要用free running clock，但我也没弄明白什么样的叫free running clock。我用的就是那些寄存器本来的时钟，如果换个时钟的话，怎么能保证采样不会出问题呢？还是不太明白，能否详细指教？谢谢啦！

greenpine

所谓的free running clock就是上电就跑的时钟，而不是依赖某些条件才有的

greenpine

看警告是说你写入的bit文件和probe文件不匹配
The device design has 0 ILA core(s) and 0 VIO core(s). The probes file has 1 ILA core(s) and 0 VIO core(s).

linghuqiubai

回复 9# greenpine

但其实是匹配的……我也不知道为啥报这个……http://forums.xilinx.com/t5/Design-Tools-Others/ILA-issues-with-Vivado-2014-3/td-p/539271
Xilinx论坛上有很多类似的问题，貌似跟时钟有点儿关系，给debug core专门生成了一个时钟，但还是不管用