VHDL 端口映射问题求助

603426333 · 发表于 2015-5-13 13:49:34

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x

现需要将多个switch连成网络，switch的实体声明和package 如下

entity Switch_Top is
port( clk : in bit;
rst : in bit;
Switch_nodeID : in bit_vector(3 downto 0);
-- port connected with former switch
--0=Nor; 1=Sou; 2=Wst; 3=Est; 4=Loc
chsel_data_in_array : in Node_data_arraytype:= (others => ('0',B"0000",B"0000",'0','0',(others =>'0')));
chsel_wrt_array_in : in Node_sig_arraytype;
chsel_avl_RT_array_out : out Node_sig_arraytype;
chsel_avl_BE_array_out : out Node_sig_arraytype;
-- port connected with next switch
arb_avl_RT_array_in : in Node_sig_arraytype;
arb_avl_BE_array_in : in Node_sig_arraytype;
arb_wrt_array_out : out Node_sig_arraytype;
arb_ch_out_array : out Node_data_arraytype:= (others => ('0',B"0000",B"0000",'0','0',(others =>'0')))
);
end entity Switch_Top;

复制代码

package Switch_Package is
constant PAYLOAD_WIDTH : integer:= 73;
constant Address_WIDTH : integer:= 4;
constant FIFO_DEPTH : integer:= 4;
constant x : integer:= 4;
constant y : integer:= 4;
constant switch_number : integer:=x*y;
type Node_ch_type is record
valid : bit;
SrcnodeID : bit_vector(3 downto 0);
--"0000"North, "0001"South, "0010"West, "0011"East, "0100" Local
DstnodeID : bit_vector(3 downto 0);
--"0000"North, "0001"South, "0010"West, "0011"East, "0100" Local
Trsf_Mode : bit;
-- transfer mode: '1' real-time (high-priority), '0' best-effort (low-priority)
Last : bit;
-- reserve for burst mode, not realized in DME yet
Payload : bit_vector(PAYLOAD_WIDTH-1 downto 0);
-- data in form of package to be transferred
end record;
type Node_sig_arraytype is array (0 to 4) of bit;
type Node_data_arraytype is array (0 to 4) of Node_ch_type; --connect different switchs
type Node_sig_arrow_arraytype is array (0 to 4, 0 to 4) of bit; --connect arbiters and FIFOs
type Node_data_arrow_arraytype is array (0 to 4, 0 to 4) of Node_ch_type;
type Ram_Data_array is array (0 to FIFO_DEPTH-1) of Node_ch_type;
type TAG_array is array (0 to 3) of integer;
type ABCD is (A, B, C, D);
type ABCD_sig_type is array (ABCD) of bit;
type ABCD_ch_type is array (ABCD) of Node_ch_type;
type nodeID is array (0 to switch_number-1) of bit_vector(0 to 3);
type net_sig_array is array (0 to switch_number-1) of bit;
type net_data_array is array (0 to switch_number-1) of Node_ch_type;
type net_sig_arrow_array is array (0 to switch_number-1 , 0 to 3) of bit;
type net_data_arrow_array is array (0 to switch_number-1, 0 to 3) of Node_ch_type;
end package Switch_Package;

复制代码

简化的网络的顶层文件代码及modelsim报错如下，跪求大神帮忙看看有什么问题应该如何修改

library ieee,std;
use ieee.std_logic_1164.all;
use std.standard.all;
use work.Switch_Package.all;
entity Net_Top is
port( clk : in bit;
rst : in bit;
Switch_nodeID : in nodeID;
--0=Nor; 1=Sou; 2=Wst; 3=Est; 4=Loc
switch_data_in_array : in net_data_array:= (others => ('0',B"0000",B"0000",'0','0',(others =>'0')));
switch_wrt_array_in : in net_sig_array;
switch_avl_RT_array_out : out net_sig_array;
switch_avl_BE_array_out : out net_sig_array;
switch_avl_RT_array_in : in net_sig_array;
switch_avl_BE_array_in : in net_sig_array;
switch_wrt_array_out : out net_sig_array;
switch_ch_out_array : out net_data_array:= (others => ('0',B"0000",B"0000",'0','0',(others =>'0')))
);
end entity Net_Top;
architecture behav of Net_Top is
signal data_switch_arrow_array : net_data_arrow_array;
signal avl_BE_switch_arrow_array : net_sig_arrow_array;
signal avl_RT_switch_arrow_array : net_sig_arrow_array;
signal wrt_switch_arrow_array : net_sig_arrow_array;
--"0 to switch_number-1" express nodeID "0 to 3" express n,s,w,e
begin
list_array1:for j in 0 to y-1 generate
first_node1:if (j=0) generate
switch:entity work.Switch_Top(behav)
port map
( clk => clk,
rst => rst,
Switch_nodeID => Switch_nodeID(0),
chsel_data_in_array(4) => switch_data_in_array(0),
chsel_wrt_array_in (4) => switch_wrt_array_in (0),
chsel_avl_RT_array_out(4) => switch_avl_RT_array_out(0),
chsel_avl_BE_array_out(4) => switch_avl_BE_array_out(0),
arb_avl_RT_array_in(4) => switch_avl_RT_array_in (0),
arb_avl_BE_array_in(4) => switch_avl_BE_array_in (0),
arb_wrt_array_out (4) => switch_wrt_array_out(0),
arb_ch_out_array (4) => switch_ch_out_array (0),
chsel_data_in_array(0) => data_switch_arrow_array(1,0),
chsel_wrt_array_in(0) => wrt_switch_arrow_array (1,0),
arb_avl_RT_array_in(0) => avl_RT_switch_arrow_array(1,0),
arb_avl_BE_array_in(0) => avl_BE_switch_arrow_array(1,0),
chsel_avl_RT_array_out(0) => avl_RT_switch_arrow_array(0,1),
chsel_avl_BE_array_out(0) => avl_BE_switch_arrow_array(0,1),
arb_wrt_array_out(0) => wrt_switch_arrow_array(0,1),
arb_ch_out_array(0) => data_switch_arrow_array(0,1),
chsel_data_in_array(3) => data_switch_arrow_array(0,3),
chsel_wrt_array_in (3) => wrt_switch_arrow_array (0,3),
arb_avl_RT_array_in(3) => avl_RT_switch_arrow_array(0,3),
arb_avl_BE_array_in(3) => avl_BE_switch_arrow_array(0,3),
chsel_avl_RT_array_out(3) => avl_RT_switch_arrow_array(4,2),
chsel_avl_BE_array_out(3) => avl_BE_switch_arrow_array(4,2),
arb_wrt_array_out(3) => wrt_switch_arrow_array(4,2),
arb_ch_out_array(3) => data_switch_arrow_array(4,2)
);
end generate first_node1;
last_node1:if(j=y-1) generate
switch:entity work.Switch_Top(behav)
port map
( clk => clk,
rst => rst,
Switch_nodeID => Switch_nodeID(j),
chsel_data_in_array(4) => switch_data_in_array(j),
chsel_wrt_array_in (4) => switch_wrt_array_in (j),
chsel_avl_RT_array_out(4) => switch_avl_RT_array_out(j),
chsel_avl_BE_array_out(4) => switch_avl_BE_array_out(j),
arb_avl_RT_array_in(4) => switch_avl_RT_array_in (j),
arb_avl_BE_array_in(4) => switch_avl_BE_array_in (j),
arb_wrt_array_out (4) => switch_wrt_array_out(j),
arb_ch_out_array (4) => switch_ch_out_array (j),
chsel_data_in_array(1) => data_switch_arrow_array(j,1),
chsel_wrt_array_in (1) => wrt_switch_arrow_array (j,1),
arb_avl_RT_array_in(1) => avl_RT_switch_arrow_array(j,1),
arb_avl_BE_array_in(1) => avl_BE_switch_arrow_array(j,1),
chsel_avl_RT_array_out(1) => avl_RT_switch_arrow_array(j-1,0),
chsel_avl_BE_array_out(1) => avl_BE_switch_arrow_array(j-1,0),
arb_wrt_array_out(1) => wrt_switch_arrow_array(j-1,0),
arb_ch_out_array(1) => data_switch_arrow_array(j-1,0),
chsel_data_in_array(3) => data_switch_arrow_array(j,3),
chsel_wrt_array_in (3) => wrt_switch_arrow_array (j,3),
arb_avl_RT_array_in(3) => avl_RT_switch_arrow_array(j,3),
arb_avl_BE_array_in(3) => avl_BE_switch_arrow_array(j,3),
chsel_avl_RT_array_out(3) => avl_RT_switch_arrow_array(y+j,2),
chsel_avl_BE_array_out(3) => avl_BE_switch_arrow_array(y+j,2),
arb_wrt_array_out(3) => wrt_switch_arrow_array(y+j,2),
arb_ch_out_array(3) => data_switch_arrow_array(y+j,2)
);
end generate last_node1;
other_node1:if(j/=0 and j/=y-1) generate
switch:entity work.Switch_Top(behav)
port map
( clk => clk,
rst => rst,
Switch_nodeID => Switch_nodeID(j),
chsel_data_in_array(4) => switch_data_in_array(j),
chsel_wrt_array_in (4) => switch_wrt_array_in (j),
chsel_avl_RT_array_out(4) => switch_avl_RT_array_out(j),
chsel_avl_BE_array_out(4) => switch_avl_BE_array_out(j),
arb_avl_RT_array_in(4) => switch_avl_RT_array_in (j),
arb_avl_BE_array_in(4) => switch_avl_BE_array_in (j),
arb_wrt_array_out (4) => switch_wrt_array_out(j),
arb_ch_out_array (4) => switch_ch_out_array (j),
chsel_data_in_array(0) => data_switch_arrow_array(j,0),
chsel_wrt_array_in (0) => wrt_switch_arrow_array(j,0),
arb_avl_RT_array_in(0) => avl_RT_switch_arrow_array(j,0),
arb_avl_BE_array_in(0) => avl_BE_switch_arrow_array(j,0),
chsel_avl_RT_array_out(0) => avl_RT_switch_arrow_array(j+1,1),
chsel_avl_BE_array_out(0) => avl_BE_switch_arrow_array(j+1,1),
arb_wrt_array_out(0) => wrt_switch_arrow_array(j+1,1),
arb_ch_out_array (0) => data_switch_arrow_array(j+1,1),
chsel_data_in_array(1) => data_switch_arrow_array(j,1),
chsel_wrt_array_in (1) => wrt_switch_arrow_array(j,1),
arb_avl_RT_array_in(1) => avl_RT_switch_arrow_array(j,1),
arb_avl_BE_array_in(1) => avl_BE_switch_arrow_array(j,1),
chsel_avl_RT_array_out(1) => avl_RT_switch_arrow_array(j-1,0),
chsel_avl_BE_array_out(1) => avl_BE_switch_arrow_array(j-1,0),
arb_wrt_array_out(1) => wrt_switch_arrow_array(j-1,0),
arb_ch_out_array (1) => data_switch_arrow_array(j-1,0),
chsel_data_in_array(3) => data_switch_arrow_array(j,3),
chsel_wrt_array_in (3) => wrt_switch_arrow_array(j,3),
arb_avl_RT_array_in(3) => avl_RT_switch_arrow_array(j,3),
arb_avl_BE_array_in(3) => avl_BE_switch_arrow_array(j,3),
chsel_avl_RT_array_out(3) => avl_RT_switch_arrow_array(y+j,0),
chsel_avl_BE_array_out(3) => avl_BE_switch_arrow_array(y+j,0),
arb_wrt_array_out(3) => wrt_switch_arrow_array(y+j,0),
arb_ch_out_array (3) => data_switch_arrow_array(y+j,0)
);
end generate other_node1;
end generate list_array1;
end architecture;

复制代码

** Error: C:/Users/WIN7/Documents/sunjy/Net_VHDL/Net_Top.vhd(48): (vcom-1026) Formal "chsel_data_in_array" associated individually was not in contiguous sequence.

** Error: C:/Users/WIN7/Documents/sunjy/Net_VHDL/Net_Top.vhd(49): (vcom-1026) Formal "chsel_wrt_array_in" associated individually was not in contiguous sequence.

** Error: C:/Users/WIN7/Documents/sunjy/Net_VHDL/Net_Top.vhd(50): (vcom-1026) Formal "arb_avl_RT_array_in" associated individually was not in contiguous sequence.

** Error: C:/Users/WIN7/Documents/sunjy/Net_VHDL/Net_Top.vhd(51): (vcom-1026) Formal "arb_avl_BE_array_in" associated individually was not in contiguous sequence.

** Error: C:/Users/WIN7/Documents/sunjy/Net_VHDL/Net_Top.vhd(52): (vcom-1026) Formal "chsel_avl_RT_array_out" associated individually was not in contiguous sequence.

** Error: C:/Users/WIN7/Documents/sunjy/Net_VHDL/Net_Top.vhd(53): (vcom-1026) Formal "chsel_avl_BE_array_out" associated individually was not in contiguous sequence.

** Error: C:/Users/WIN7/Documents/sunjy/Net_VHDL/Net_Top.vhd(54): (vcom-1026) Formal "arb_wrt_array_out" associated individually was not in contiguous sequence.

** Error: C:/Users/WIN7/Documents/sunjy/Net_VHDL/Net_Top.vhd(55): (vcom-1026) Formal "arb_ch_out_array" associated individually was not in contiguous sequence.

[求助] VHDL 端口映射问题求助

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[求助] VHDL 端口映射问题求助