可以用全局时钟驱动网线吗，为什么报错说会增加延迟？

zhuyuefeng2009

全局时钟资源不是应该延迟很小吗？

我的全局时钟缓冲出来的信号 作为寄存器操作的控制信号，而且这个控制信号是全局的（整个FPGA上 好多寄存器都要用到这个信号）。
//////////////////////////////下面是报错

ERRORlace:1136 - This design contains a global buffer instance, <u7>, driving
   the net, <a11>, that is driving the following (first 30) non-clock load pins.
   < PIN: u3/Mmux_SMG_Aa_in[6]_SMG_A_IN[7]_mux_2_OUT<1>11.A5; >
   < PIN: u3/Mmux_SMG_Aa_in[6]_SMG_A_IN[7]_mux_2_OUT<2>11.A5; >
   < PIN: u3/Mmux_SMG_Aa_in[6]_SMG_A_IN[7]_mux_2_OUT<3>11.A5; >
   < PIN: u3/Mmux_SMG_Aa_in[6]_SMG_A_IN[7]_mux_2_OUT<4>11.A5; >
   < PIN: u3/Mmux_SMG_Aa_in[6]_SMG_A_IN[7]_mux_2_OUT<5>11.A5; >
   < PIN: u3/Mmux_SMG_Aa_in[6]_SMG_A_IN[7]_mux_2_OUT<6>11.A5; >
   < PIN: u3/Mmux_SMG_Aa_in[6]_SMG_A_IN[7]_mux_2_OUT<7>11.A5; >
   < PIN: u3/SMG_CONTROL_IN_inv1_INV_0.A6; >
   This is not a recommended design practice in Spartan-6 due to limitations in
   the global routing that may cause excessive delay, skew or unroutable
   situations.  It is recommended to only use a BUFG resource to drive clock
   loads. If you wish to override this recommendation, you may use the
   CLOCK_DEDICATED_ROUTE constraint (given below) in the .ucf file to demote
   this message to a WARNING and allow your design to continue.
   < PIN "u7.O" CLOCK_DEDICATED_ROUTE = FALSE; >

jun_dahai

报告中已经描述的很清楚了，并且已经告诉你可以使用BUFG替代