oc8051学习笔记

shixha

开贴学习oc8051, 目的有两个: 1笔记作为记录  2 发帖赚信元 哈哈

shixha

1 opencore上下载 oc8051的verilog代码
2下载L斑竹的资料, 在我的黑金开发板上实现http://download.csdn.net/detail/leishangwen/5173363

shixha

1 重复做两遍, 按照<DE2上使用OC8051运行点灯程序（一）>文档做, 功能仿真就不对, p1_out值始终是复位后的0xff     Softwere: Quartus 11.0  ModelSim SE-64 10.0c


2 尝试直接运行使用资料中的quartus 工程, 跑功能仿真, 观察p1_out的值, 也没有实现每隔一段时间+1的功能, 应该是有问题的




瞬间迷茫了, 照葫芦画瓢失败, 希望不是软件的问题

shixha

看一些文档, 了解下oc8051的基本运行机制, 数据通路等  现在连怎么去debug都没有思路, 笨

oc8051自带的文档, oc8051 Design Document, 8051 Core Specification 文档和trunk中verilog的实现, 稍微有点不同, 应该是根据早期版本写的文档, 比如没有wb总线的有关接口, 没有BIST


几个兼容性的概念
binary compatible: run the same executable code, exactly the same layout of interrupt service routines, I/O-ports, hardware registers, counter/timers, external interfaces and so on
source compatible: must be recompiled or  need a interpreter
backward compatible: older executable code will run unchanged on newer hardware or software

8051 feature
boolean processing: useful in industrial control application
4 bank working register: quickly interrupt service and context switch( subroutine call)

oc8051 VS original 8051
1> two stage pipeline, so all instructions (except jumps ) can be executed in one clock period
2> 256 bytes of on-chip data memory, SFRs and general-purpose memory share same address space
3> separate connection for input and output ports and every special function has its own pin

shixha

默认defines情况下,看下模块之间的关系

Module Hierarchy
oc8051_top

• oc8051_deocder

               oc8051_multiply
               oc8051_divide

• oc8051_alu
• oc8051_ram_top

               oc8051_ram_256x8_two_bist

• oc8051_alu_src_sel
• oc8051_comp
• oc8051_cy_select
• oc8051_indi_addr
• oc8051_memory_interface
• oc8051_sfr

               oc8051_acc                oc8051_b_register
               oc8051_sp
               oc8051_dptr
               oc8051_psw
               oc8051_ports
               oc8051_uart
               oc8051_int
               oc8051_tc
               oc8051_tc2
(Not included  module)

• oc8051_rom
• oc8051_icache

               oc8051_ram_64x32_dual_bist
               oc8051_cache_ram (not used)

• oc8051_wb_iinterface

以上模块层次和oc8051 Design Document中的模块关系不一样, 重新封装成oc8051_alu_src, oc8051_sfr,oc8051_memory_interface 等模块, 减少了顶层模块的数量, 连接关系更清晰了, 可能对后面PR, 时序收敛也有帮助



分享雷斑竹的oc8051_top模块连接图
oc8051模块连接图.pdf (131.77 KB, 下载次数: 167 )

2014-7-30 20:46 上传

点击文件名下载附件

shixha

继续<DE2上使用OC8051运行点灯程序（一）>
功能仿真的bug找到了, mif文件的单位问题, 默认是UNS, View>memory radix>hexadecimal  修改为16进制
另外修改两处不疼不痒的地方,
oc8051_ram_256x8_two_bist.v中 126行 修改为ifdef OC8051_RAM_Altera
oc8051_tb.v  82行 修改为 wbi_err_i=1'b0;   wbi_err_i应该是1 bit reg




明天继续, 回去睡觉

shixha

LVTTL与LVCMOS (cyclone IV)
3.3V LVTTL：
Vcc：3.3V；VOH>=2.4V；VOL<=0.45V；VIH>=1.7V；VIL<=0.8V
3.3V LVCMOS：
Vcc：3.3V；VOH>=3.1V；VOL<=0.2V；VIH>=1.7V；VIL<=0.8V

3.0V LVTTL：
Vcc：3.0V；VOH>=2.4V；VOL<=0.45V；VIH>=1.7V；VIL<=0.8V

3.0V LVCMOS：
Vcc：3.0V；VOH>=2.8V；VOL<=0.2V；VIH>=1.7V；VIL<=0.8V


TTL与COMS电路比较
TTL速度快, 延时短, 功耗大, 噪声容限小; COMS速度慢, 延时长, 功耗低, 噪声容限大

VREF group:
A group of I/O pins associated with a VREF pin that are grouped for the purpose of specifying voltage. Each VREF group is associated with a specific I/O bank, and all of the pins in a VREF group must use the same VREF voltage.

shixha

parallel_case 和 full_case 使用问题

// synopsys parallel_case
if a case statement is not "parallel", remove priority encoder logic when synthesized.
a funcitional mismatch  between RTL simulation and gate-level simulation.

// synopsys full_case
if a case statement is not "full', remove the latch when synthesized and the outputs are "don't care's" for all unspecified case items.
a funcitional mismatch  between RTL simulation and gate-level simulation.



Best Guidelines
1> do not use "full_case parallel_case" directives with any Verilog case staments
2> incomplete case statements should have default case assignment
3> do not assign "x" value in default case assigment
4> When coding a case statement with "don't cares," use a casez statement and use "?" characters instead of "z" characters in the case items to indicate "don't care" bits.
5> Do not use casex for synthesizable code
6> Code all intentional priority encoders using if-else-if statements

shixha

继续<DE2上使用OC8051运行点灯程序（一>


oc8051默认剪裁情况下有168个pin, 超过cyclone IV 166个 user io, 所以关掉UART, 减少两个pin




分配引脚
set_global_assignment -name RESERVE_ALL_UNUSED_PINS "AS INPUT TRI-STATED"

#40M
set_location_assignment
PIN_A9
-to wb_clk_i
set_location_assignment
PIN_M1
-to i_wb_rst_i

#connect to GND
set_location_assignment PIN_R8  -to i_wbd_ack_i
set_location_assignment PIN_E1  -to i_wbi_ack_i
set_location_assignment PIN_T8  -to i_wbd_err_i
set_location_assignment PIN_M2  -to i_wbi_err_i

#connect to 3.3V
set_location_assignment PIN_T9  -to  ea_in

set_location_assignment PIN_J1  -to  p1_o[0]
set_location_assignment PIN_J2  -to  p1_o[1]
set_location_assignment PIN_K1  -to  p1_o[2]
set_location_assignment PIN_K2  -to  p1_o[3]





wbd_ack_i, wbi_ack_i, wbd_err_i, wbi_err_i 取反引出为i_wbd_ack_i, i_wbi_ack_i, i_wbd_err_i, i_wbi_err_i信号, 并分配到4个按键pin上, 因为4个按键pin默认是高电平, 这样取反获得低电平的输入了;   同样wb_rst_i取反引出为i_wb_rst_i信号, 因为板子上的reset是低电平有效;   时钟分配为40M;   ea_in引到一个默认高电平的按键pin上以此来获得高电平输入;  p1_o低4位分配给LED[0..4]四个引脚;  其余unused pins 设为
"AS INPUT TRI-STATED";



去掉代码中所有//synopsys full_case parallel_case 语句, 增加default语句, 直到quartus不报warnning, 否则如文档中说的, 门及仿真会有问题, 这个原因8#已经详细介绍

Quartus中编译, 获得延时信息, 选择slow -8 1.2V 85 Model, 进行门级仿真, 正确



下载到黑金开发板, 4个LED, 显示" 亮 暗 亮 暗" 正确

<DE2上使用OC8051运行点灯程序（一>在黑金开发板上实现

MOFANA

:)