TSMC DRC及LVS 警告问题

zzk1010322

基于TSMC做了一个运放的版图，进行DRC检查时出现很多下述错误：
Check CSR.R.1.NWELLi {@ If customer request TSMC to add CSR，seal ring and CDU,empty areas at 4 chips corners must be reserved and no layout is allowed inside.   EMPTY_AREA AND NWELLi}
Check CSR.R.1.POPLYGi {@ If customer request TSMC to add CSR，seal ring and CDU,empty areas at 4 chips corners must be reserved and no layout is allowed inside.   EMPTY_AREA AND POPLYGi}
Check CSR.R.1.PIMPi {@ If customer request TSMC to add CSR，seal ring and CDU,empty areas at 4 chips corners must be reserved and no layout is allowed inside.   EMPTY_AREA AND PIMPi}
Check CSR.R.1.NIMPi {@ If customer request TSMC to add CSR，seal ring and CDU,empty areas at 4 chips corners must be reserved and no layout is allowed inside.   EMPTY_AREA AND NIMPi}
Check CSR.R.1.CONTi {@ If customer request TSMC to add CSR，seal ring and CDU,empty areas at 4 chips corners must be reserved and no layout is allowed inside.   EMPTY_AREA AND CONTi}
.....
....
忽略上述错误做LVS时，虽然露出笑脸，验证通过，但是在 Exteaction Results中提示下述Warning：
WARNING: Invalid PATHCHK request " ! POWER": no POWER nets present, operation aborted.

WARNING: Invalid PATHCHK request " ! GROUND": no GROUND  nets present, operation aborted.

WARNING: Invalid PATHCHK request "GROUND && ! POWER": no POWER nets present, operation aborted.


WARNING: Invalid PATHCHK request "POWER && ! GROUND": no POWER nets present, operation aborted.


WARNING: Invalid PATHCHK request "! POWER && ! GROUND": no POWER nets present, operation aborted.

哪位大侠遇到过这种问题，请指教

zzk1010322

LVS的warning已解决，是因为自己在电源和地命名的时候用的“VDDA”和“GNDA” 在.lvs文件中不识别，更改.lvs文件把这连个符号加进去就ok了。 DRC的问题依然待解决......

zzk1010322

继续求解答......

duke_wang

highlight的地方如果要求加CSR，seal ring and CDU，4个角的地方就空着不能画layout

小小天地

楼主问题解决了吗？我也遇到同样的DRC问题，不知道该怎么弄。希望会的大神们不吝赐教，谢谢

ime_t

同遇到这个问题，不知楼主解决没有，或者有没有大神帮忙解决一下，谢谢

icfbicfb

define full_chip 关闭， 如果不是chip是block的话，请不要开这个选项

检查corner pad的，有corner pad才行

zh1898

原则上chip corner的区域是不可以放一些电路功能的layout，除非之前有以身试法过

icfbicfb

corner很有讲究的， 不是随便那么设计的，

jswbianca

涨涨人气