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本帖最后由 yangkaiqu 于 2013-11-24 18:00 编辑
本人才开始学习assertion,今天编写一个assertion的时候,老是编译通不过,具体代码如下:
`timescale 1ns / 1ns
module ldo_1p8_assertion(
input ldo_pd,
input rstb_3v,
input real ldo_out
);
parameter delay_ldo_pd_check = 5;
reg sample_clk;
always #100 sample_clk = ~ sample_clk;
initial begin
sample_clk = 1'b0;
end
property ldo_pd_assert;
@(posedge sample_clk )
(rstb_3v) |->
if (ldo_pd)
( ##delay_ldo_pd_check (ldo_out < 0.005))
else
( ##delay_ldo_pd_check ((ldo_out > 1.795) && (ldo_out < 1.805)));
endproperty
ldo_pd: assert property (ldo_pd_assert)
else
$display("Assertion ERROR: the ldo_pd_assert has been failed at the time @%t",$time);
cover_ldo_pd_assert: cover property (ldo_pd_assert);
endmodule
用irun 来进行编译的时候,老是报错:
file: ldo_1p8_assertion.sv
if (ldo_pd)
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ncvlog: *E,BOOLOP (ldo_1p8_assertion.sv,23|13): Expected a verilog expression as operand to property if/else operator.
module worklib.ldo_1p8_assertion:sv
errors: 1, warnings: 0
这是怎么回事啊?更改了代码好多遍,试验了好多次,都要报错。
急求高人指点啊。。。。。。。 |
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