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因为生成的异或门SDF带posedge信息,而元件库的specify是不用posedge的延时(直接输入输出延时),导致MIX-SIGNAL后仿找不到PATH,上网查了下,可以利用PT反标SDF,用-noedge指令去掉posedge,但是发现用PT读取.sdf发生以下错误,求大神拯救。我的U4/out是一个分频功能,因为.sdf后仿会跑飞,所以设置了一个create_generated_clock -name TXCLK_10M -divide_by 10 -source vco_in [get_pins U4/out]时钟进行fix hold操作修复,我觉得应该是这个问题(没设以前都可以读取,而且报的error位置也与这吻合),求大神指导我哪里没操作好,已经折腾两个多月了,再搞不出来要被老师逐出门户了,求大神指点我一下。先谢过各位大神了,以下是PT反馈的信息。
pt_shell> read_sdf /home/user0/cgm/cgm_extracted.sdf
Error: Net delay from pin 'U4/NI01D5_G2B1I1/Y' to pin 'NI01D3_G3IP/A'
cannot be
annotated because of a timing assertion on hierarchical pin 'U4/out'. (PTE-015)
Error: Net delay from pin 'U4/NI01D5_G2B1I1/Y' to pin 'U3/counter_reg/CKB'
cannot be
annotated because of a timing assertion on hierarchical pin 'U4/out'. (PTE-015)
Error: Net delay from pin 'U4/NI01D5_G2B1I1/Y' to pin 'U3/out_reg/CK'
cannot be
annotated because of a timing assertion on hierarchical pin 'U4/out'. (PTE-015)
****************************************
Report : read_sdf /home/user0/cgm/cgm_extracted.sdf
-load_delay cell
-analysis_type on_chip_variation
-min_type sdf_min
-max_type sdf_max
Design : cgm
Version: C-2009.06-SP3
Date : Thu Nov 14 22:27:24 2013
****************************************
3 error(s)
Number of annotated cell delay arcs : 153
Number of annotated net delay arcs : 122
Number of annotated timing checks : 108
Number of annotated constraints : 54
TEMPERATURE: 25.00 (min) 25.00 (max)
VOLTAGE : 5.00 (min) 5.00 (max)
PROCESS : TYPICAL (min) TYPICAL (max) |
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