异步复位同步释放，对复位信号的约束问题

yuweilian

异步复位同步释放代码
module arst_syn (
   input wire clk,
   input wire arst,
   output reg rst_syn
);
reg rff1;
    always @(posedge clk or negedge arst)
    begin:rst_syn_block
      if (!arst) begin
        {rst_syn,rff1} <= 2'b0;
      end
      else begin
        {rst_syn,rff1} <= {rff1,1'b1};
      end
    end
endmodule


我的core代码
/*--------------------------------------------------
*--------------------------------------------------*/
module core (
           input wire clk,
      input wire rst_n,
input wire dvalid,
input wire [2:0] data_i,
output wire [2:0] d0h
     );
  wire rst_syn;
arst_syn M_arst_syn(
  .clk(clk),
  .arst(rst_n),
  .rst_syn(rst_syn)
);

  get_samp_value M_get_samp_value
(
  .clk(clk),
  .rst_n(rst_syn),
.dvalid_i(dvalid),
.data_i(data_i),
  .d0h_o(d0h)
);
         
endmodule

对于此core的复位，有以下两个约束，那个合适哪
1对rst_syn 设置成set_ideal network
set_ideal_latency 4.0 [get_ports rst_n]
set_ideal_transition 2.0 [get_ports rst_n]
set_ideal_network -no_propagate [get_net M_arst_syn/rst_syn]

2 对 rst_n设置成set_ideal_network
set_ideal_network [get_ports rst_n]

还是有其他更好的哪