A Spur-Frequency-Boosting PLL With a −74 dBc Reference-Spur Suppression

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A Spur-Frequency-Boosting PLL With a −74 dBc Reference-Spur Suppression in 90 nm Digital CMOS
Mohamed M. Elsayed, Member, IEEE, Mohammed Abdul-Latif, and Edgar Sánchez-Sinencio, Life Fellow, IEEE

Abstract—An architectural solution for designing a low-reference-
spur PLL is proposed. A spur-frequency boosting block is inserted
between the phase-frequency detector and the charge pump
to boost the charge pump input frequency. Hence, the spur at the
reference frequency is eliminated and is frequency-boosted to a
higher frequency, , at which the PLL gain is much less resulting
in greater suppression. Quantitative analysis of the charge pump
spurs is presented to clarify the different tradeoffs affecting the
output spurs level. The proposed technique breaks the classical
trade off between the different PLL parameters. It adds a degree of
freedom in PLL design to reduce the reference spur level without
reducing neither the loop bandwidth nor the voltage-controlled oscillator’s
gain (K ). A 3.6 GHz PLL prototype is fabricated
using UMC 90 nm digital CMOS technology. A −74 dBc reference-
spur suppression is measured along with a (K /ω ) ratio
of 16.67 and a (ω /ω ) ratio of 1/20. The proposed architecture
provides additional spur suppression of 30 dB compared to a
conventional PLL and, to the best of the authors’ knowledge, this
PLL provides the best normalized reference-spur rejection in literature.
The prototype occupies 0.063 mm2.
Index Terms—Phase locked loop, PLL, reference spurs, spurs,
frequency synthesizers, time-to-voltage converters, voltage-to-time
converters, low spurs, spur boosting, spur regeneration.

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