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发表于 2011-1-7 17:47:46
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回复 52# zhjjwzz
看看這是不是你需要的?
Most likely the logic high level (5.0 V) needs to be adjusted.
The reference level in the ideal ADC and DAC model also needs to be adjusted. |
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DAC_DNL_INL_IDEAL_ADC.rar
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DAC, INL & DNL Verilog-A code, + ideal ADC Verilog-A code
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