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楼主: gavin168

请教下DAC的DNL, INL仿真问题

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发表于 2010-7-17 15:39:59 | 显示全部楼层
you can use vector give dac code
发表于 2010-8-5 10:17:59 | 显示全部楼层
请大大高手给个仿真用的verilog-a的程序,谢谢!
发表于 2010-8-5 21:28:15 | 显示全部楼层
所以到底要怎麼測DNL INL
发表于 2010-8-31 20:55:21 | 显示全部楼层
我很想知道,希望大牛人指点啊
发表于 2010-8-31 20:58:40 | 显示全部楼层
不要用Verilog,在Cadence中怎么测INL和DNL 啊,O(∩_∩)O谢谢
发表于 2010-10-16 09:49:38 | 显示全部楼层
mixed sig ic test and measument这本书上的程序可以测试INL和DNL
发表于 2010-11-30 14:20:44 | 显示全部楼层
可以一看
发表于 2010-12-23 10:59:22 | 显示全部楼层
关注……
发表于 2011-1-6 14:07:50 | 显示全部楼层
最近测试很头疼
发表于 2011-1-7 17:19:26 | 显示全部楼层
Several ways to appraoch

0. derivation of INL and DNL by analytical equations (not exactly simulation)

1. 100% behavioral simulation by MATLAB, focusing on the impact of device mismatch to INL/DNL.
In the MATLAB code, the critical components are assigned with random variables.
Multiple simulations are needed since each time, the INL and DNL will be different.

2. SPICE circuit simulation without mismatch taken into account (given corret clock and appropriate settling time, the calculated INL and DNL should be very small (e.g., DNL < 0.1 LSB for DNL, INL < 0.5 LSB).

3. SPICE circuit simulation with mismtach taken into account (i.e., Monte Carlo simulation)

For case 2 and case 3, an ideal ADC (model) is needed.
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