generate不属于sv的新特性,是verilog2001的新特性
在IEEE std1364-2001手册中可以查到,帮忙贴一段,如下(其它相关的lz可以自己搜一下):
genvar i;
generate
case ({MEM_SIZE, MEM_WIDTH})
{32’d8, 32’d16}: // 8Meg 16 bits wide.
begin
for (i=0;i<4;i = i + 1)
begin:word
sms_16b216t0 p
(.clk(clk), .csb(csx), .cke(cke), .ba(ba[0]),
.addr(adr[10:0]),...rasb(rasx), .casb(casx),
.web(wex),.udqm(dqm[2*i+1]), .ldqm(dqm[2*i]),
...dqi(data[15+16*i:16*i]), .dev_id(dev_id3[4:0])
);
end
task read_mem;
input [31:0] address;
output [63:0] data;
begin
word[3].p.read_mem(address, data[63:48]);
word[2].p.read_mem(address, data[47:32]);
word[1].p.read_mem(address, data[31:16]);
word[0].p.read_mem(address, data[15:0]);
end
endtask
end
// The generated instance names are word[3].p, word[2].p,
// word[1].p, word[0].p, and the task read_mem
{32’d16, 32’d8}: // 16Meg 8 bits wide.
begin
for (i=0;i<4;i = i + 1)
begin:byte
sms_16b208t0 p
(.clk(clk), .csb(csx), .cke(cke), .ba(ba[0]),
.addr(adr[10:0]),
...rasb(rasx), .casb(casx), .web(wex), .dqm(dqm[i]),
.dqi(data[8+8*i:8*i]),...dev_id(dev_id7[4:0])
);
end
task read_mem;
input [31:0] address;
output [63:0] data;
begin
byte[7].p.read_mem(address, data[63:56]);
byte[6].p.read_mem(address, data[55:48]);
byte[5].p.read_mem(address, data[47:40]);
byte[4].p.read_mem(address, data[39:32]);
byte[3].p.read_mem(address, data[31:24]);
byte[2].p.read_mem(address, data[23:16]);
byte[1].p.read_mem(address, data[15:8]);
byte[0].p.read_mem(address, data[7:0]);
end
endtask
.....
endcase
endgenerate |