Relationship between latencies of a generated clock and its master clock

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Question:
How is the total clock latency calculated under different conditions of generated clock and the master/source clock?Here is the clock circuit in question, which has a clock divider flip-flop (U1) that drives another flip-flop U2. The master clock is named 'MCLK' and the generated clock is named 'GCLK'.            

Answer:  The total clock network latency calculated by Prime Time depends upon the nature of the master and generated clock -- whether ideal or propagated, the network latencies, and whether there is a user-specified source latency for the generated clock. The following table summarizes how the latencies of the master clock and the generated clocks are used in different network conditions to calculate the total clock network latency.

Master Clock	Source Clock	Generated Clock Source Latency (GCSL)	Total clock network latency (TNL)
Propagated	Propagated	Not Specified	MCSL+MCNL+GCNL
Propagated	Propagated	User Specified	GCSL+GCNL (MCSL and MCNL are ignored)
Propagated	Ideal	Not Specified	MCSL+MCNL+GCNL
Propagated	Ideal	User Specified	GCSL+GCNL (MCSL and MCNL are ignored)
Ideal	Propagated	Not Specified	GCNL ( MCSL and MCNL are ignored )
Ideal	Propagated	User Specified	GCSL+GCNL ( MCSL and MCNL are ignored )
Ideal	Ideal	Not Specified	GCNL ( MCSL and MCNL are ignored )
Ideal	Ideal	User Specified	GCSL+GCNL ( MCSL and MCNL are ignored )

Legend:     MCSL : Master Clock Source Latency
                   MCNL : Master Clock Network Latency
                   GCSL : Generated Clock Source Latency
                   GCNL : Generated Clock Network Latency

Highlights of the summary:
1. User-specified Generated Clock Latency controls whether or not the master    clock latency will be used for calculation of total clock network latency.    User-specified Source Latency on generated clock isloates the generated    clock network from the latencies of the master clock network.
2. If master clock is declared ideal, the latencies in the master clock    netowrk will not come into calculation of total network latency. For    example, if you declare master clock ideal, and annotate a delay on the    master clock network, the annotated delay will not be used in calculation    of total netowrk latency.
3. Setting latency on a propagated clock makes it an ideal clock. Removing the    latency does not automatically make a propagated clock an ideal clock.
4. If both master clock and generated clock are declared propagated, the total    network latency will be sum of latencies in the master clock network and    latencies in the generated clock network, as long as there is no user-   specified source latency on the generated clock network. In case the user    has specified a source clock latency on the generated clock, the latencies    in the master clock network will be ingnored and only latencies in the    generated clock will be used for total network latency calculation.
5. Users can specify source latency by the command set_clock_latency -source.
6. Useful commands for analyzing clock network and latencies are:   
(a) report_clock -attributes -skew   
(b) report_clock_timing -type latency -verbose
7. Specifiying source latency sets the startpoint for delay calculation in   the network.

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