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通过CPLD来控制一个五位的八段数码管显示,显示数字300,我分别用三种有细微差别的方法实现,发现效果不同;一、用一个模块实现,代码如下:
- module xianshi(out1,out2,out3,out4,out5,di);
- //input [16:0] in;
- output wire [7:0] out1,out2,out3,out4,out5;
- output wire [9:0] di;
- wire [3:0] num5,num4,num3,num2,num1;
- reg [7:0] temp1,temp2,temp3,temp4,temp5;
- assign di=10'd0;
- assign num5=300/10000;
- assign num4=(300-num5*10000)/1000;
- assign num3=(300-num5*10000-num4*1000)/100;
- assign num2=(300-num5*10000-num4*1000-num3*100)/10;
- assign num1=300-num5*10000-num4*1000-num3*100-num2*10;
- parameter num_0=8'b11100111;
- parameter num_1=8'b00100001;
- parameter num_2=8'b11001011;
- parameter num_3=8'b01101011;
- parameter num_4=8'b00101101;
- parameter num_5=8'b01101110;
- parameter num_6=8'b11101110;
- parameter num_7=8'b00100011;
- parameter num_8=8'b11101111;
- parameter num_9=8'b00101111;
- case(num5)
- 0:assign out5=num_0;
- 1:assign out5=num_1;
- 2:assign out5=num_2;
- 3:assign out5=num_3;
- 4:assign out5=num_4;
- 5:assign out5=num_5;
- 6:assign out5=num_6;
- 7:assign out5=num_7;
- 8:assign out5=num_8;
- 9:assign out5=num_9;
- endcase
- case(num4)
- 0:assign out4=num_0;
- 1:assign out4=num_1;
- 2:assign out4=num_2;
- 3:assign out4=num_3;
- 4:assign out4=num_4;
- 5:assign out4=num_5;
- 6:assign out4=num_6;
- 7:assign out4=num_7;
- 8:assign out4=num_8;
- 9:assign out4=num_9;
- endcase
- case(num3)
- 0:assign out3=num_0;
- 1:assign out3=num_1;
- 2:assign out3=num_2;
- 3:assign out3=num_3;
- 4:assign out3=num_4;
- 5:assign out3=num_5;
- 6:assign out3=num_6;
- 7:assign out3=num_7;
- 8:assign out3=num_8;
- 9:assign out3=num_9;
- endcase
- case(num2)
- 0:assign out2=num_0;
- 1:assign out2=num_1;
- 2:assign out2=num_2;
- 3:assign out2=num_3;
- 4:assign out2=num_4;
- 5:assign out2=num_5;
- 6:assign out2=num_6;
- 7:assign out2=num_7;
- 8:assign out2=num_8;
- 9:assign out2=num_9;
- endcase
- case(num1)
- 0:assign out1=num_0;
- 1:assign out1=num_1;
- 2:assign out1=num_2;
- 3:assign out1=num_3;
- 4:assign out1=num_4;
- 5:assign out1=num_5;
- 6:assign out1=num_6;
- 7:assign out1=num_7;
- 8:assign out1=num_8;
- 9:assign out1=num_9;
- endcase
- endmodule
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这种方法正确;
二、用两个模块实现,利用实例化,代码如下:
- module pulse_counter(out1,out2,out3,out4,out5,di);
- output wire[7:0] out1,out2,out3,out4,out5;
- output wire [9:0] di;
- xianshi u_xianshi(3000,out1,out2,out3,out4,out5,di);
- endmodule
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- module xianshi(in,out1,out2,out3,out4,out5,di);
- input [16:0] in;
- output reg [7:0] out1,out2,out3,out4,out5;
- output [9:0] di;
- wire [3:0] num5,num4,num3,num2,num1;
- reg [7:0] temp1,temp2,temp3,temp4,temp5;
- reg di=10'd0;
- assign num5=in/10000;
- assign num4=(in-num5*10000)/1000;
- assign num3=(in-num5*10000-num4*1000)/100;
- assign num2=(in-num5*10000-num4*1000-num3*100)/10;
- assign num1=in-num5*10000-num4*1000-num3*100-num2*10;
- parameter num_0=8'b11100111;
- parameter num_1=8'b00100001;
- parameter num_2=8'b11001011;
- parameter num_3=8'b01101011;
- parameter num_4=8'b00101101;
- parameter num_5=8'b01101110;
- parameter num_6=8'b11101110;
- parameter num_7=8'b00100011;
- parameter num_8=8'b11101111;
- parameter num_9=8'b00101111;
- always @(in)
- begin
- case(num5)
- 0: out5=num_0;
- 1: out5=num_1;
- 2: out5=num_2;
- 3: out5=num_3;
- 4: out5=num_4;
- 5: out5=num_5;
- 6: out5=num_6;
- 7: out5=num_7;
- 8: out5=num_8;
- 9: out5=num_9;
- endcase
- case(num4)
- 0: out4=num_0;
- 1: out4=num_1;
- 2: out4=num_2;
- 3: out4=num_3;
- 4: out4=num_4;
- 5: out4=num_5;
- 6: out4=num_6;
- 7: out4=num_7;
- 8: out4=num_8;
- 9: out4=num_9;
- endcase
- case(num3)
- 0: out3=num_0;
- 1: out3=num_1;
- 2: out3=num_2;
- 3: out3=num_3;
- 4: out3=num_4;
- 5: out3=num_5;
- 6: out3=num_6;
- 7: out3=num_7;
- 8: out3=num_8;
- 9: out3=num_9;
- endcase
- case(num2)
- 0: out2=num_0;
- 1: out2=num_1;
- 2: out2=num_2;
- 3: out2=num_3;
- 4: out2=num_4;
- 5: out2=num_5;
- 6: out2=num_6;
- 7: out2=num_7;
- 8: out2=num_8;
- 9: out2=num_9;
- endcase
- case(num1)
- 0: out1=num_0;
- 1: out1=num_1;
- 2: out1=num_2;
- 3: out1=num_3;
- 4: out1=num_4;
- 5: out1=num_5;
- 6: out1=num_6;
- 7: out1=num_7;
- 8: out1=num_8;
- 9: out1=num_9;
- endcase
- end
- endmodule
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在pulse_counter模块中调用xianshi模块,xianshi模块中的输出变量采用的是reg型;
经实践,该方法正确;
三、用两个模块实现,利用实例化,和方法二区别在于在xianshi模块中输出变量采用wire类型,代码如下:
- module pulse_counter(out1,out2,out3,out4,out5,di);
- output wire[7:0] out1,out2,out3,out4,out5;
- output wire [9:0] di;
- xianshi u_xianshi(3000,out1,out2,out3,out4,out5,di);
- endmodule
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- module xianshi(in,out1,out2,out3,out4,out5,di);
- input [16:0] in;
- output wire [7:0] out1,out2,out3,out4,out5;
- output [9:0] di;
- wire [3:0] num5,num4,num3,num2,num1;
- reg [7:0] temp1,temp2,temp3,temp4,temp5;
- reg di=10'd0;
- assign num5=in/10000;
- assign num4=(in-num5*10000)/1000;
- assign num3=(in-num5*10000-num4*1000)/100;
- assign num2=(in-num5*10000-num4*1000-num3*100)/10;
- assign num1=in-num5*10000-num4*1000-num3*100-num2*10;
- parameter num_0=8'b11100111;
- parameter num_1=8'b00100001;
- parameter num_2=8'b11001011;
- parameter num_3=8'b01101011;
- parameter num_4=8'b00101101;
- parameter num_5=8'b01101110;
- parameter num_6=8'b11101110;
- parameter num_7=8'b00100011;
- parameter num_8=8'b11101111;
- parameter num_9=8'b00101111;
- case(num5)
- 0: assign out5=num_0;
- 1: assign out5=num_1;
- 2: assign out5=num_2;
- 3: assign out5=num_3;
- 4: assign out5=num_4;
- 5: assign out5=num_5;
- 6: assign out5=num_6;
- 7: assign out5=num_7;
- 8: assign out5=num_8;
- 9: assign out5=num_9;
- endcase
- case(num4)
- 0: assign out4=num_0;
- 1: assign out4=num_1;
- 2: assign out4=num_2;
- 3: assign out4=num_3;
- 4: assign out4=num_4;
- 5: assign out4=num_5;
- 6: assign out4=num_6;
- 7: assign out4=num_7;
- 8: assign out4=num_8;
- 9: assign out4=num_9;
- endcase
- case(num3)
- 0: assign out3=num_0;
- 1: assign out3=num_1;
- 2: assign out3=num_2;
- 3: assign out3=num_3;
- 4: assign out3=num_4;
- 5: assign out3=num_5;
- 6: assign out3=num_6;
- 7: assign out3=num_7;
- 8: assign out3=num_8;
- 9: assign out3=num_9;
- endcase
- case(num2)
- 0: assign out2=num_0;
- 1: assign out2=num_1;
- 2: assign out2=num_2;
- 3: assign out2=num_3;
- 4: assign out2=num_4;
- 5: assign out2=num_5;
- 6: assign out2=num_6;
- 7: assign out2=num_7;
- 8: assign out2=num_8;
- 9: assign out2=num_9;
- endcase
- case(num1)
- 0: assign out1=num_0;
- 1: assign out1=num_1;
- 2: assign out1=num_2;
- 3: assign out1=num_3;
- 4: assign out1=num_4;
- 5: assign out1=num_5;
- 6: assign out1=num_6;
- 7: assign out1=num_7;
- 8: assign out1=num_8;
- 9: assign out1=num_9;
- endcase
- endmodule
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经试验,这种方法无法得到预期效果;需要达到3.3V,数码管才能发亮,但是方法三的实行结果只能是每个引脚都处于一点几伏的状态。
求教!! |
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