SystemVerilog For Design 2nd Edition

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SystemVerilog For Design
A Guide to Using SystemVerilog for Hardware Design and Modeling

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Foreword ................................................................................................................. xxi
Preface ................................................................................................................... xxiii
Target audience...................................................................................................................... xxiii
Topics covered........................................................................................................................xxiv
About the examples in this book..............................................................................................xxv
Obtaining copies of the examples...........................................................................................xxvi
Example testing.......................................................................................................................xxvi
Other sources of information .................................................................................................xxvii
Acknowledgements..................................................................................................................xxx
Chapter 1: Introduction to SystemVerilog...............................................................1
1.1     SystemVerilog origins.......................................................................................................1
1.1.1     Generations of the SystemVerilog standard.......................................................2
1.1.2     Donations to SystemVerilog ..............................................................................4
1.2     Key SystemVerilog enhancements for hardware design...................................................5
1.3     Summary ...........................................................................................................................6
Chapter 2: SystemVerilog Declaration Spaces ........................................................7
2.1     Packages  ...........................................................................................................................8
2.1.1     Package definitions ............................................................................................9
2.1.2     Referencing package contents..........................................................................10
2.1.3     Synthesis guidelines .........................................................................................14
2.2     $unit compilation-unit declarations.................................................................................14
2.2.1     Coding guidelines.............................................................................................17
2.2.2     SystemVerilog identifier search rules ..............................................................17
2.2.3     Source code order.............................................................................................17
2.2.4     Coding guidelines for importing packages into $unit ......................................19
2.2.5     Synthesis guidelines .........................................................................................25
2.3     Declarations in unnamed statement blocks .....................................................................26
2.3.1     Local variables in unnamed blocks ..................................................................27
2.4     Simulation time units and precision ................................................................................28
2.4.1     Verilog’s timescale directive............................................................................28
2.4.2     Time values with time units .............................................................................30
2.4.3     Scope-level time unit and precision .................................................................31viii
2.4.4     Compilation-unit time units and precision.......................................................32
2.5     Summary .........................................................................................................................34
Chapter 3: SystemVerilog Literal Values and Built-in Data Types.....................37
3.1     Enhanced literal value assignments.................................................................................38
3.2     ‘define enhancements ......................................................................................................39
3.2.1     Macro argument substitution within strings.....................................................39
3.2.2     Constructing identifier names from macros.....................................................41
3.3     SystemVerilog variables..................................................................................................42
3.3.1     Object types and data types..............................................................................42
3.3.2     SystemVerilog 4-state variables.......................................................................43
3.3.3     SystemVerilog 2-state variables.......................................................................44
3.3.4     Explicit and implicit variable and net data types .............................................47
3.3.5     Synthesis guidelines .........................................................................................48
3.4     Using 2-state types in RTL models .................................................................................48
3.4.1     2-state type characteristics ...............................................................................49
3.4.2     2-state types versus 2-state simulation.............................................................49
3.4.3     Using 2-state types with case statements .........................................................51
3.5     Relaxation of type rules...................................................................................................52
3.6     Signed and unsigned modifiers .......................................................................................55
3.7     Static and automatic variables.........................................................................................56
3.7.1     Static and automatic variable initialization ......................................................59
3.7.2     Synthesis guidelines for automatic variables ...................................................60
3.7.3     Guidelines for using static and automatic variables.........................................61
3.8     Deterministic variable initialization ................................................................................61
3.8.1     Initialization determinism ................................................................................61
3.8.2     Initializing sequential logic asynchronous inputs ............................................65
3.9     Type casting ....................................................................................................................67
3.9.1     Static (compile time) casting............................................................................67
3.9.2     Dynamic casting...............................................................................................69
3.9.3     Synthesis guidelines .........................................................................................70
3.10   Constants .........................................................................................................................71
3.11   Summary .........................................................................................................................72
Chapter 4: SystemVerilog User-Defined and Enumerated Types .......................75
4.1     User-defined types...........................................................................................................75
4.1.1     Local typedef definitions..................................................................................76
4.1.2     Shared typedef definitions................................................................................76
4.1.3     Naming convention for user-defined types ......................................................78
4.2     Enumerated types ............................................................................................................79
4.2.1     Enumerated type label sequences.....................................................................83ix
4.2.2     Enumerated type label scope............................................................................83
4.2.3     Enumerated type values ...................................................................................84
4.2.4     Base type of enumerated types.........................................................................85
4.2.5     Typed and anonymous enumerations...............................................................86
4.2.6     Strong typing on enumerated type operations..................................................86
4.2.7     Casting expressions to enumerated types.........................................................88
4.2.8     Special system tasks and methods for enumerated types.................................89
4.2.9     Printing enumerated types................................................................................92
4.3     Summary .........................................................................................................................93
Chapter 5: SystemVerilog Arrays, Structures and Unions ..................................95
5.1     Structures.........................................................................................................................96
5.1.1     Structure declarations.......................................................................................97
5.1.2     Assigning values to structures..........................................................................98
5.1.3     Packed and unpacked structures.....................................................................101
5.1.4     Passing structures through ports.....................................................................104
5.1.5     Passing structures as arguments to tasks and functions .................................105
5.1.6     Synthesis guidelines .......................................................................................105
5.2     Unions ...........................................................................................................................105
5.2.1     Unpacked unions............................................................................................106
5.2.2     Tagged unions ................................................................................................108
5.2.3     Packed unions.................................................................................................109
5.2.4     Synthesis guidelines .......................................................................................111
5.2.5     An example of using structures and unions ...................................................111
5.3     Arrays ............................................................................................................................113
5.3.1     Unpacked arrays.............................................................................................113
5.3.2     Packed arrays .................................................................................................116
5.3.3     Using packed and unpacked arrays ................................................................118
5.3.4     Initializing arrays at declaration.....................................................................119
5.3.5     Assigning values to arrays .............................................................................121
5.3.6     Copying arrays ...............................................................................................123
5.3.7     Copying arrays and structures using bit-stream casting.................................124
5.3.8     Arrays of arrays..............................................................................................125
5.3.9     Using user-defined types with arrays.............................................................126
5.3.10   Passing arrays through ports and to tasks and functions................................127
5.3.11   Arrays of structures and unions......................................................................128
5.3.12   Arrays in structures and unions......................................................................128
5.3.13   Synthesis guidelines .......................................................................................128
5.3.14   An example of using arrays............................................................................129
5.4     The foreach array looping construct..............................................................................130x
5.5     Array querying system functions ..................................................................................132
5.6     The $bits “sizeof” system function ...............................................................................134
5.7     Dynamic arrays, associative arrays, sparse arrays and strings ......................................135
5.8     Summary .......................................................................................................................136
Chapter 6: SystemVerilog Procedural Blocks, Tasks and Functions ................137
6.1     Verilog general purpose always procedural block ........................................................138
6.2     SystemVerilog specialized procedural blocks...............................................................142
6.2.1     Combinational logic procedural blocks .........................................................142
6.2.2     Latched logic procedural blocks ....................................................................150
6.2.3     Sequential logic procedural blocks ................................................................152
6.2.4     Synthesis guidelines .......................................................................................152
6.3     Enhancements to tasks and functions............................................................................153
6.3.1     Implicit task and function statement grouping...............................................153
6.3.2     Returning function values ..............................................................................153
6.3.3     Returning before the end of tasks and functions............................................154
6.3.4     Void functions................................................................................................155
6.3.5     Passing task/function arguments by name .....................................................156
6.3.6     Enhanced function formal arguments ............................................................157
6.3.7     Functions with no formal arguments..............................................................158
6.3.8     Default formal argument direction and type ..................................................158
6.3.9     Default formal argument values.....................................................................159
6.3.10   Arrays, structures and unions as formal arguments .......................................160
6.3.11   Passing argument values by reference instead of copy..................................161
6.3.12   Named task and function ends .......................................................................165
6.3.13   Empty tasks and functions .............................................................................166
6.4     Summary .......................................................................................................................166
Chapter 7: SystemVerilog Procedural Statements..............................................169
7.1     New operators................................................................................................................170
7.1.1     Increment and decrement operators ...............................................................170
7.1.2     Assignment operators.....................................................................................173
7.1.3     Equality operators with don’t care wildcards.................................................176
7.1.4     Set membership operator — inside ................................................................178
7.2     Operand enhancements..................................................................................................180
7.2.1     Operations on 2-state and 4-state types..........................................................180
7.2.2     Type casting ...................................................................................................180
7.2.3     Size casting.....................................................................................................181
7.2.4     Sign casting ....................................................................................................182
7.3     Enhanced for loops........................................................................................................182
7.3.1     Local variables within for loop declarations..................................................183xi
7.3.2     Multiple for loop assignments........................................................................185
7.3.3     Hierarchically referencing variables declared in for loops ............................185
7.3.4     Synthesis guidelines .......................................................................................186
7.4     Bottom testing do...while loop ......................................................................................186
7.4.1     Synthesis guidelines .......................................................................................188
7.5     The foreach array looping construct..............................................................................188
7.6     New jump statements — break, continue, return ..........................................................188
7.6.1     The continue statement ..................................................................................190
7.6.2     The break statement .......................................................................................190
7.6.3     The return statement.......................................................................................191
7.6.4     Synthesis guidelines .......................................................................................192
7.7     Enhanced block names ..................................................................................................192
7.8     Statement labels.............................................................................................................194
7.9     Enhanced case statements .............................................................................................195
7.9.1     Unique case decisions ....................................................................................196
7.9.2     Priority case statements..................................................................................199
7.9.3     Unique and priority versus parallel_case and full_case.................................201
7.10   Enhanced if...else decisions...........................................................................................203
7.10.1   Unique if...else decisions ...............................................................................203
7.10.2   Priority if decisions ........................................................................................205
7.11   Summary .......................................................................................................................206
Chapter 8: Modeling Finite State Machines with SystemVerilog ......................207
8.1     Modeling state machines with enumerated types..........................................................208
8.1.1     Representing state encoding with enumerated types .....................................210
8.1.2     Reversed case statements with enumerated types..........................................211
8.1.3     Enumerated types and unique case statements...............................................213
8.1.4     Specifying unused state values.......................................................................214
8.1.5     Assigning state values to enumerated type variables.....................................216
8.1.6     Performing operations on enumerated type variables....................................218
8.2     Using 2-state types in FSM models...............................................................................219
8.2.1     Resetting FSMs with 2-state and enumerated types ......................................219
8.3     Summary .......................................................................................................................221
Chapter 9: SystemVerilog Design Hierarchy.......................................................223
9.1     Module prototypes.........................................................................................................224
9.1.1     Prototype and actual definition ......................................................................225
9.1.2     Avoiding port declaration redundancy...........................................................225
9.2     Named ending statements..............................................................................................226
9.2.1     Named module ends.......................................................................................226
9.2.2     Named code block ends .................................................................................226xii
9.3     Nested (local) module declarations ...............................................................................227
9.3.1     Nested module name visibility.......................................................................230
9.3.2     Instantiating nested modules ..........................................................................231
9.3.3     Nested module name search rules ..................................................................232
9.4     Simplified netlists of module instances.........................................................................233
9.4.1     Implicit  .name port connections....................................................................238
9.4.2     Implicit  .*  port connection ...........................................................................242
9.5     Net aliasing....................................................................................................................244
9.5.1     Alias rules.......................................................................................................245
9.5.2     Implicit net declarations.................................................................................246
9.5.3     Using aliases with .name and .* .....................................................................247
9.6     Passing values through module ports ............................................................................251
9.6.1     All types can be passed through ports............................................................251
9.6.2     Module port restrictions in SystemVerilog ....................................................252
9.7     Reference ports..............................................................................................................255
9.7.1     Reference ports as shared variables ...............................................................256
9.7.2     Synthesis guidelines .......................................................................................256
9.8     Enhanced port declarations ...........................................................................................257
9.8.1     Verilog-1995 port declarations ......................................................................257
9.8.2     Verilog-2001 port declarations ......................................................................257
9.8.3     SystemVerilog port declarations ....................................................................258
9.9     Parameterized types.......................................................................................................260
9.10   Summary .......................................................................................................................261
Chapter 10: SystemVerilog Interfaces..................................................................263
10.1   Interface concepts..........................................................................................................264
10.1.1   Disadvantages of Verilog’s module ports ......................................................268
10.1.2   Advantages of SystemVerilog interfaces .......................................................269
10.1.3   SystemVerilog interface contents ..................................................................273
10.1.4   Differences between modules and interfaces.................................................273
10.2   Interface declarations ....................................................................................................274
10.2.1   Source code declaration order........................................................................276
10.2.2   Global and local interface definitions ............................................................276
10.3   Using interfaces as module ports...................................................................................277
10.3.1   Explicitly named interface ports ....................................................................277
10.3.2   Generic interface ports ...................................................................................278
10.3.3   Synthesis guidelines .......................................................................................278
10.4   Instantiating and connecting interfaces .........................................................................278
10.5   Referencing signals within an interface ........................................................................279
10.6   Interface modports.........................................................................................................28110.6.1   Specifying which modport view to use..........................................................282
10.6.2   Using modports to define different sets of connections.................................286
10.7   Using tasks and functions in interfaces .........................................................................288
10.7.1   Interface methods ...........................................................................................289
10.7.2   Importing interface methods ..........................................................................289
10.7.3   Synthesis guidelines for interface methods....................................................292
10.7.4   Exporting tasks and functions ........................................................................293
10.8   Using procedural blocks in interfaces ...........................................................................296
10.9   Reconfigurable interfaces..............................................................................................296
10.10 Verification with interfaces ...........................................................................................298
10.11 Summary .......................................................................................................................299
Chapter 11: A Complete Design Modeled with SystemVerilog..........................301
11.1   SystemVerilog ATM example.......................................................................................301
11.2   Data abstraction.............................................................................................................302
11.3   Interface encapsulation..................................................................................................305
11.4   Design top level: squat ..................................................................................................308
11.5   Receivers and transmitters.............................................................................................315
11.5.1   Receiver state machine...................................................................................315
11.5.2   Transmitter state machine ..............................................................................318
11.6   Testbench.......................................................................................................................321
11.7   Summary .......................................................................................................................327
Chapter 12: Behavioral and Transaction Level Modeling .................................329
12.1   Behavioral modeling .....................................................................................................330
12.2   What is a transaction?....................................................................................................330
12.3   Transaction level modeling in SystemVerilog ..............................................................332
12.3.1   Memory subsystem example..........................................................................333
12.4   Transaction level models via interfaces ........................................................................335
12.5   Bus arbitration ...............................................................................................................337
12.6   Transactors, adapters, and bus functional models.........................................................341
12.6.1   Master adapter as module...............................................................................341
12.6.2   Adapter in an interface ...................................................................................348
12.7   More complex transactions ...........................................................................................353
12.8   Summary .......................................................................................................................354
Appendix A: The SystemVerilog Formal Definition (BNF) ...............................355
Appendix B: Verilog and SystemVerilog Reserved Keywords...........................395
Appendix C: A History of SUPERLOG, the Beginning of SystemVerilog .......401
Index ........................................................................................................................415

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