SNUG Israel, 2004

s8319

Israel, 2004

1st Place - Best Paper
[size=-1]Using VERA Random Constrain Engine to Test Complex MPEG4 Chips	[size=-1]Doron Meiraz - Emblaze Semiconductor Gal Algavish - Independent	[size=-1]Paper	[size=-1]Presentation


A1 - Functional Verification Techniques



[size=-1]Paper Title	[size=-1]Author(s)	[size=-1]Paper	[size=-1]Presentation
[size=-1]ABV (Assertion Based Verification) - From concept to Reality via OVA	[size=-1]Ilan Lisha, Doron Stein - CSI - Cisco Systems Israel	[size=-1]Paper	[size=-1]Presentation
[size=-1]Complex SoC Validation using Synopsys DesignWare Verification IP and Vera	[size=-1]Tomer Labin - Discretix	[size=-1]N/A	[size=-1]Presentation
[size=-1]Using VERA Random Constrain Engine to Test Complex MPEG4 Chips	[size=-1]Doron Meiraz - Emblaze Semiconductor Gal Algavish - Independent	[size=-1]Paper	[size=-1]Presentation


A2 - Analog Verification Techniques



[size=-1]Paper Title	[size=-1]Author(s)	[size=-1]Paper	[size=-1]Presentation
[size=-1]Full Custom SRAM Design for Multimedia Application in 0.18u	[size=-1]Oren Katzir, Kobi Steiner, Gadi Lehana - Silicon Design Systems LTD	[size=-1]Paper	[size=-1]Presentation
[size=-1]Mixed Signal Verification Methodology Using NanoSim Integration with VCS	[size=-1]Shmuel Zagury, Shmuel Tachan - Tower Semiconductor	[size=-1]Paper	[size=-1]Presentation


B1- Physical Design 1



[size=-1]Paper Title	[size=-1]Author(s)	[size=-1]Paper	[size=-1]Presentation
[size=-1]Dune Networks Implementation of Filp Chip Design in 130 nm Technology	[size=-1]Zachi Feldman - Dune Networks	[size=-1]Paper	[size=-1]Presentation
[size=-1]Multi Power VDD Flow for Complex Designs	[size=-1]Leonid Tsukerman, Rafi Zagury - Intel - PTK	[size=-1]Paper	[size=-1]Presentation
[size=-1]The Challenge of a Complex Chip Level Routing using the Columbia/AstroIU	[size=-1]Eli Kraus - Analog Devices Israel DSP	[size=-1]Paper	[size=-1]Presentation


B2 - Physical Design 2



[size=-1]Paper Title	[size=-1]Author(s)	[size=-1]Paper	[size=-1]Presentation
[size=-1]Automatic DFM Flow for Unit Level using Hercules & Apollo	[size=-1]Albert Yankelovich - Mellanox	[size=-1]Paper	[size=-1]Presentation
[size=-1]From RTL to GDS using Synopsys Flow Within Less Than 10 Weeks	[size=-1]Yaron Lavi - Intel ICGH	[size=-1]Paper	[size=-1]Presentation


C1 - Physical Synthesis



[size=-1]Paper Title	[size=-1]Author(s)	[size=-1]Paper	[size=-1]Presentation
[size=-1]ECO Flow - Using Physical Compiler	[size=-1]Niv Margalit - CSI - Cisco System Israel	[size=-1]Paper	[size=-1]Presentation
[size=-1]Minimum Physical Constraints in Physical Synthesis Flow	[size=-1]Roy Bar - ParthusCeva Inc	[size=-1]N/A	[size=-1]Presentation
[size=-1]Secrets of High-Speed Design or How to Reach 1.0 GHz Cycle Time with 0.13 um Technology	[size=-1]Oleg Milter - Intel Corporation	[size=-1]Paper	[size=-1]Presentation


C2 - Design for Test



[size=-1]Paper Title	[size=-1]Author(s)	[size=-1]Paper	[size=-1]Presentation
[size=-1]A Hold-Buffer Reduction Algorithm for Scan-Chain Timing Closure	[size=-1]Alex Bronfer, Rafy Diaz, Max Nigri - Texas Instruments Short Distance Wireless Israel	[size=-1]Paper	[size=-1]Presentation
[size=-1]Failure Analysis by TetraMAX-Diagnosis	[size=-1]Benny Rosen - Independent	[size=-1]N/A	[size=-1]Presentation


Paper Only



[size=-1]Paper Title	[size=-1]Author(s)	[size=-1]Paper	[size=-1]Presentation
[size=-1]Custom Aligners Clock Tree Methodology Using Physical Compiler	[size=-1]Dan Saad, Yossi Asher - Motorola Semiconductors Israel, VLSI DSP	[size=-1]Paper	[size=-1]N/A


Keynote Speech



[size=-1]Speech Title	[size=-1]Speaker
[size=-1]SNUG Israel 2004 Keynote: Tough Techonomics!	[size=-1]Dr Aart de Geus - Chairman of the Board & CEO - Synopsys Inc


Tutorial Presentation



[size=-1]Session	[size=-1]Tutorial Title	[img][/img]
[size=-1]TA	[size=-1]Galaxy Implementation Platform - DC, Jupiter, PC and Astro Update	[size=-1]TA
[size=-1]TB	[size=-1]Static Timing Analysis, Signal Integrity and Equivalence Checking Updates	[size=-1]TB
[size=-1]TC	[size=-1]Discovery Verification Platform - Assertions, Vera and Magellan Update	[size=-1]TC
[size=-1]TD	[size=-1]Analog Design and Simulation Environment	[size=-1]TD

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s8319

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s8319

上传太麻烦了 能把人累死
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s8319

上传太麻烦了 能把人累死
搞一ftp行不行？

s8319

上传太麻烦了 能把人累死
搞一ftp行不行？

s8319

上传太麻烦了 能把人累死
搞一ftp行不行？

s8319

上传太麻烦了 能把人累死
搞一ftp行不行？

s8319

上传太麻烦了 能把人累死
搞一ftp行不行？