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[资料] 2004 DesignCon Proceedings

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发表于 2012-5-19 14:43:11 | 显示全部楼层 |阅读模式

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发表于 2012-5-20 18:32:44 | 显示全部楼层
要是有个目录就好了
 楼主| 发表于 2012-5-22 16:05:35 | 显示全部楼层
目录内容

Track One: Chip-level Physical Design

1-TA1        RLDRAM: Features and Applications of the Ubiquitous Low-Latency/High-Bandwidth DRAM
       
        Thomas J. Pawlowski, Micron Technology

1-TA2        10M Gate SoC Implementation

        Rune Jensen, ReShape
        Thomas O’Dwyer, Phillips Semiconductors

1-TA3        Parameterized Global Modeling of Planar Inductor

        Guan-Huei See, Universiti Teknologi Malaysia
        Albert Victor Kordesch, Silterra Malaysia Sdn Bhd
        Mazlina Esa, Universiti Teknologi Malaysia

1-TP1        The Necessary Link for Design Closure: LVS-Parasitic Extraction

        John Ferguson, Mentor Graphics

1-TP2        Breaking Down Barriers To SOC Integration with Three-Dimensional Integrated Circuits

        Robert Markunas, Ziptronix

1-WA1        Front-end RTL Hand-off flows, Audits and Considerations for ASIC Physical Design

        Ramesh Banda, Agere Systems
        Anil Kapoor, Agere Systems
        Che-Tsung Chen, Agere Systems

1-WA2        PCI/PCI-X Interface Design Considerations

        Michael Shay, Vitesse Semiconductor
        Archie Hu, Vitesse Semiconductor

1-WP1        Case Studies on Improving FPGA Performance using Physical Synthesis

        Rich Faris, Mentor Graphics
        Dan DeVries, Mentor Graphics
        Anil Khanna, Mentor Graphics
        John MacDonald, Mentor Graphics

1-WP2        Full-Chip Signal and Power Integrity with Silicon Substrate Effect

        Norio Matsui, Applied Simulation Technology
        Dileep Divekar, Applied Simulation Technology
        Neven Orhanovic, Applied Simulation Technology
        Hiroshi Wabuka, NEC Corporation

Track Two: Functional and IP Design

2-TA1        SoC Design Challenges: The Need for System Modeling and IP Integration

        Imed Moussa, TNI-Valiosys
        Richard Hersemeul, TNI Valiosys

2-TA2        Low-Power Design - Don't Forget About the Memory
        (Available at http://www.designcon.com/conference/papers.html)

        Jud Bond, MoSys

2-TA3        Multi-core Embedded Debug for Structured ASIC Systems

        Neal Stollen, First Silicon Solutions
        Rick Leatherman, First Silicon Solutions
        Bruce Ableidinger, First Silicon Solutions
        Ernie Edgar, First Silicon Solutions

2-TP1        TLM Bus Verification for RTL Compliance

        Petr Tomiczek, CoWare

2-TP2        Improving Application Performance With Instruction Set Architecture Extensions To Embedded Processor

        Jonah Probell, Ultra Data

2-WA1        Effective Verilog RTL coding Guidelines for "Coding for Coverage"

        Hani Saleh, Synopsys
        Peter Gillen, Synopsys


2-WA2.1        Can IP Quality be Objectively Measured?

        Kathy Werner, Mentor Graphics


2-WA2.2        High-performance Java Virtual Machine, easily scalable to your low-power mobile embedded systems hardware

        Oliver Garreau, Nazomi Communications


2-WP1        VHDL-200X and the Future of VHDL

        Jim Lewis, SynthWorks
        Stephen Bailey, Mentor Graphic’s Model Technology Group
        Erich Marschner, Cadence Design Systems
        J. Bhasker, eSilicon Corp.
        Peter Ashenden, Ashenden Designs Pty. Ltd.


2-WP2        System Solutions Based On Multiple, Small And Optimized DSP Cores Offer The Best Of Both Worlds

        Louay M.A. Jalloul, Infineon Technologies Morphics
        Daniel Martin, Infineon Technologies


Track Three: Functional Verification

3-TA1        Emulating/Prototyping a Network Device in a Live Network

        Bob Zeidman, Zeidman Consulting


3-TA2        Verifying a Cryptographic Processor using a Smart Bus Functional Model

        Alfonso Iniguez, Motorola SPS


3-TA3        Functional Verification in the Context of Design Reuse

        Thomas L. Anderson, Virtual Socket Interface Alliance (VSIA)


3-TP1        On-chip HDTV Test Pattern Generators Enhance System and Device Testing

        James A. Mears, National Semiconductor


3-TP2        A Custom Hardware/Software Co-verification Solution for the Design and Development of a High Speed Digital Oscilloscope Acquisition System

        Stony Yakovac, Tektronix
        Andrew Iverson, Tektronix
        Brian Crofts, Tektronix
        John Dierks, Tektronix
        David Hite, Tektronix

3-WA1.1        Overcoming the Verification Hurdle for PCI Express

        Lawrence Loh, Jasper Design Automation
        Howard Wong-Toi, Jasper Design Automation
        C. Norris Ip, Jasper Design Automation
        Harry Foster, Jasper Design Automation
        Douglas Perry, Jasper Design Automation

3-WA1.2        Bluetooth Transceiver Design: A Top-Down Flow for Complex RF Mixed-Signal ICs

        Rami Ahola, Spirea AB
        Daniel Wallner, Spirea AB
        Marius Sida, Mentor Graphics
        Avi Gupta, Mentor Graphics


3-WA2        What is the true cost of Lint?

        Adam Krolnik, LSI Logic Corporation
        Lionel Bening, Hewlett-Packard


3-WP1        Formal Verification of Block-Level Requirements

        Harry Foster, Jasper Design Automation
        C. Norris Ip, Jasper Design Automation
        Howard Wong-Toi, Jasper Design Automation
        Douglas Perry, Jasper Design Automation


3-WP2        An Effective Approach to Translate System Models into Hardware Verification Models using Real-Time
        (Available at http://www.designcon.com/conference/papers.html)

        Vijay Subramanian, Legerity
        Bill Luo, Legerity


Track Four: High-Speed Timing, Jitter and Noise

4-TA1        Testing High Speed Serial IO Interfaces Based on Spectral Jitter Decomposition

        Rainer Plitschka, Agilent Technologies
        Bernd Laquai, Agilent Technologies



4-TA2        Using Measure-Based Modeling to Extract Backplane Deterministic Jitter

        Alfred P. Neves, TDA Systems

4-TA3        Statistical and Sensitivity Analysis of Voltage and Timing Budgets of Multi-Gigabit Interconnect Systems

        Wendem T. Beyene, Rambus
        Newton Chang, Rambus
        June Feng, Rambus
        Chuck Yuan, Rambus


4-TP1        Statistical and System Transfer Function Based Method For Jitter and Noise In Communication Design and Test

        Mike Li, PhD., Wavecrest Corporation
        Jan Wilstrup, Wavecrest Corporation


4-TP2        Jitter Separation at Data Rates Above 3 Gb/s

        Neal Buren, Agilent Technologies
        Megan Chura, Agilent Technologies
        Greg LeCheminant, Agilent Technologies
        Jim Stimple, Agilent Technologies
        Marlin Viss, Agilent Technologies


4-WP1        Controlled Eye Pattern Test And Analysis

        David Brunker, Molex Corporation
        Patrick Casher, Molex Corporation
        Farah Haddadin, Molex Corporation


4-WP2        Use the Right Model for the Simulation of Multi-Gigabit Channels

        Weston Beal, Mentor Graphics


Track Five: Power Distribution and Low-Power Design

5-WA1        Design of World's Smallest Video Decoder

        Xiaodong Wu, Texas Instruments
        Erkan Bilhan, Texas Instruments
        Rajitha Padakanti, Texas Instruments
        Prakash Jayasekaran, Texas Instruments
        Eric Lian, Texas Instruments
        Viet Dinh, Texas Instruments
        Dallas White, Texas Instruments       
        Jason Meiners, Texas Instruments
        Hardar Bilhan, Texas Instruments


5-WA2        System Level Power Integrity Analysis and Correlation for Multi-Gigabit Designs

        Ralf Schmitt, Ph.D., Rambus
        Xuejue Huang, Ph.D., Rambus
        Ling Yang, Rambus
        Chuck Yuan, Ph.D., Rambus


5-WP1        Investigating Via and Discrete Capacitor Effects

        Kun Zhang, Huawei Technologies Co.
Zhen Mu, Cadence Design Systems
        Heiko Dudek, Cadence Design Systems


5-WP2        Modeling Noise on a Printed Circuit Board Power Plane

        John Grebenkemper, Hewlett-Packard


Track Six: Chip and Package Co-Design

6-TA1        A 6.4 Gb/s SERDES Design in a Low-Cost, High Density Buildup Package

        Kevin Roselle, Bayside Design
        C. Thomas Gray, Cadence Design Systems
        Daniel Lambalot, Bayside Design
        Jason Oversmith, Bayside Design
        Jason Thurston, Cadence Design Systems
        Terry Perkinson, Cadence Design Systems


6-TA2        Simulation, Design, and Measurements of a High-Performance BGA Package

        Andrew Byers, Tektronix
        Laudie Doubrava, Tektronix


6-TA3        ASIC Package Characterization And Correlation With Simulation

        Wheling Cheng, Cisco Systems
        John Fisher, Cisco Systems
        Gurpreet Hundal, Cisco Systems
        Zhiping Yang, Cisco Systems


6-TP1        Package and Test Environment Design for a 10 Gigabit Ethernet Transceiver

        Haw-Jyh Liaw, Aeluros
        C. Patrick Yue, Aeluros
        Roger Emigh, STATS
        Dong Hun Shin, Ansoft Corp.


6-TP2        Enhancing the performance of wirebonded organic BGA packages through package codesign- Case study:12.5 Gbit/sec 16:1 Multiplexer with clock generator.

        Ozgur Misman, Amkor Technology
        Moses Chan, Vitesse Semiconductor
        Kicheol Bae, Amkor Technology


Track Seven: High-Speed Interconnects

7-TA3        Tempus-6000: A Signal Integrity Revolution in Surface Mount Backplane Connectors and SPICE/S-Parameter

        Edward Sayre, North East Systems Associates
        Edward Sayre III, North East Systems Associates
        Scott Mickievicz, ITT Industries, Canon
        Michael Baxter, North East Systems Associates


7-TP1        Obtaining Accurate Device-Only S-Parameter data to 15-20 GHz Using In-Fixture Measurement Techniques

        Chad Morgan, Tyco Electronics


7-TP2        Utilizing TDR and VNA Data to Develop 4-port Frequency Dependent Models

        Jim Mayrand, Consultant
        Mike Resso, Agilent Technologies
        Dima Smolyansky, TDA Systems


7-WA1        Making S-parameter Data Suitable for SPICE Modeling

        Jan De Geest, Ph.D., FCI CDC
        Stefaan Sercu, Ph.D., FCI CDC
        Craig Clewell, FCI CDC
        Jim Nadolny, FCI CDC


7-WA2        The Impact of Environmental Conditions on Channel Performance

        Greg Sheets, Agere Systems
        John D’Ambrosia, Tyco Electronics


7-WP1        Channel Compliance Testing Utilizing Novel Statistical Eye Methodology

        Anthony Sanders, Infineon Technologies
        Mike Resso, Agilent Technologies


7-WP2        A Rigorous Approach to High Speed Interconnect Characterization and Model Correlation through Differential TDR
        (Available at http://www.designcon.com/conference/papers.html)

        John Rettig, Tektronix
        John Carlson, Tektronix

Track Eight: Discrete Components and Vias

8-WA1        Method For Optimizing A 10 Gb/S PCB Signal Launch

        Martin Vogel, Ansoft Corporation
        Suresh Subramaniam, Xilinx
        Brad Cole, eval Solutions


8-WA2        Crosstalk In 10Gbps Serial Channels: Optimizing The Forgotten Component

        James Clink, Winchester Electronics
        Chris Flaherty, Winchester Electronics


8-WP1        Developing a Working Model for Vias

        Greg Edlund, IBM Engineering and Technology Services
        Young Kwark, Watson Research Ctr.
        Christian Schuster, Watson Research Ctr.
        Lei Shan, Watson Research Ctr.


8-WP2        Modeling and Verification of Backplane Press-fit PTH Vias

        Ravi Kollipara, Rambus
        Ben Chia, Rambus


Track Nine: System Interconnect Architecture

9-TA1        Instrumentation Based Analysis of System FPGAs

        Judd E. Heape, QuickLogic Corporation
        Neal Stollon, First Silicon Solutions


9-TA2        Signal Integrity and Timing Analysis Simulation Reuse

        Robert Haller, Signal Integrity Software
        Douglas Burns, Signal Integrity Software
        Barry Katz, Signal Integrity Software


9-TA3        Design of 3.125 Gb/s Interconnect for High-Bandwidth FPGAs

        Sherri Azgomi, Altera Corporation
        Lawrence Williams, Ansoft Corporation


9-TP1        A Primer to the World of Hardware Dependant Software

        Kumar Venkatramani, Executive Consultant
        Frank Pospiech, Alcatel
        Stephen Olsen, Mentor Graphics


9-TP2        Using HyperTransport DirectPackettm Technology To Simplify Design of Packet-based Communications Equipment

        Brian Holden, PMC-Sierra

Track Ten: High-Performance Backplane Design

10-TA1        Backplane Differential Channel Microprobe Characterization in Time and Frequency Domains

        Eric Bogatin, GigaTest Labs
        Mike Resso, Agilent Technologies


10-TA2        Potential Benefits of Mixed Dielectric Stripline

        Noel Hudson, WL Gore and Associates


10-TA3        A Hybrid Measurement and Electromagnetic Field Solver Approach for the Design of High-Performance Interconnects: An Investigation of Traces and SMA Transitions

        Scott McMorrow, Teraspeed Consulting Group LLC
        Alfred Neves, TDA Systems


10-TP1        Extending the Life of Today's Backplanes thru Simultaneous Bidirectional Transmission

        Lee Harrison, KeyEye Communications
        Hiroshi Takatori, KeyEye Communications


10-TP2        Error-Correction Coding for 10Gb/s Backplane Transmission

        Lars E. Thon, Aeluros
        Haw-Jyh Liaw, Aeluros


Track Eleven: End-to-End Technologies

11-TA1        Design of a 6.25 Gbps Backplane SerDes with Top-down Design Methodology

        Song Wu, Texas Instruments
        Sridhar Ramaswamy, Texas Instruments
        Bhavesh Bhakta, Texas Instruments
        Paul Landman, Texas Instruments
        Robert Payne, Texas Instruments
        Vikas Gupta, Texas Instruments
        Bharat Parthasarathy, Texas Instruments
        Seema Deshpande, Texas Instruments
        Wai Lee, Texas Instruments


11-TA2        A High Channel-Density, Ultra-High Bandwidth Reference Backplane Designed and Manufactured for 10Gb/s NRZ Serial Signaling

        John Mitchell, Winchester Electronics/Interconnect Technologies
        Bodhi Das, Xilinx Inc.


11-TA3        Multi-Mode Memory Controllers for Network DRAM Interfaces

        Rajan Sharma, Cisco Systems
        Christophe Joly, Cisco Systems


11-TP1        SerDes Architectures and Applications

        Dave Lewis, National Semiconductor Corporation


11-TP2        End-to-End Digital Interconnect for 802.11 WLAN Sub-system Implementation
        (Available at http://www.designcon.com/conference/papers.html)

        Patrick Yu, Ali Microelectronics
        Ed Liu, NVIDIA


11-WA1        Integrating 10G Serial onto a Large Digital CMOS ASSP: Taking 10G from Lab to Production

        Edward Priest, Cortina Systems
        Mario Moy, Cortina Systems
        Robert Badal, Cortina Systems
        George Hare, 3M


11-WA2        A Flexible Backplane Serial Link for 5-10Gb in Realistic Environments

        Jared Zerbe, Rambus
        Carl Werner, Rambus
        Ravi Kollipara, Rambus
        Vladimir Stojanovic, Rambus


Track RD: Reference Design Village Papers

RD-TA1.1        A Design Kit for Developing FPGA-Based Embedded Linux Applications

        John Kerl, Avnet Design Services
        Warren Miller, Avnet Design Services


RD-TA1.2        A Reference Design Kit for JPEG 2000 Applications

        Bill Finch, CAST, Inc.
        Warren Miller, Avnet Design Services


RD-TA2.1        A Reference Design for an FPGA-Based 64-bit/133MHz PCI-X Interface

        Jim Jaksich, Avnet Design Systems


RD-TA2.2        A Design Kit for Developing FPGA-Based 10Giga-bit Ethernet Ports

        Matt Schultz, Avnet Design Services


RD-TA3.1        A Reference Design for a 3.125Giga-bit Serial Channel Using an FPGA

        James Dampare, Avnet Design Services
        Abhijit Athavale, Xilinx
        Vince Gavagan, Avnet Design Services


RD-TA3.2        A Reference Design Kit for uCLinux on a Motorola ColdFire Processor

        John Kerl, Avnet Design Services
        Warren Miller, Avnet Design Services


RD-WA1.1        A Reference Design Kit for FPGA-Based DSP Applications

        Kim Olsen, Avnet Design Services
        Warren Miller, Avnet Design Services


RD-WA1.2        An FPGA-based Embedded Processor Design Kit with Debug Methodology
        Warren Miller, Avnet Design Services


RD-WA2.1        A Reference Design Kit for a 200MHz RLDRAM Controller in a Xilinx FPGA

                Warren Miller, Avnet Design Services


RD-WA2.2        A Reference Design for a Residential Gateway using the IBM PowerPC® 405

                Carlton Heyer, Avnet Design Services
                Warren Miller, Avnet Design Services


TecForums

TF1        Signal Integrity Modeling and Simulation Tools

        Ching-Chao Huang, Optimal Corporation


TF2        VHDL Transaction Based Verification

        Jim Lewis, SynthWorks

TF4        Package Selection and Design To Meet Custom Thermal Requirements

        Jesse Galloway, Amkor Technology


TF5        Advances in Time and Frequency Domain Measurements, Modeling and Signal Integrity Analysis of Gigabit Interconnects

        Dima Smolyansky, TDA Systems


TF8        Characterizing Jitter Histograms for Clock and DataCom Applications

        John Patrin, Wavecrest
        Mike Peng Li, Wavecrest


TF9        Thin and Very Thin Laminates for Power Distribution Applications: What is New in 2004?

        Frank Alberto, SUN Microsystems
        Istvan Novack, SUN Microsystems
        David McGregor, DuPont iTechnologies
        Bill Balliette, 3M Electronic Solution Division
        John Andresakis, Oak-Mitsui Technologies
        Cindy Gretzinger, Sanmina-SCI, Oswego
        Bob Greenlee, Merix Corporation
        Lance P. Riley, Unicircuit, Inc.
        Steve Patric        Benchmark Electronics, Inc.
        John Grebenkemper, NonStop Enterprise Division, Hewlett Packard Technologies


TF10        Advances in Design, Modeling, Simulation and Measurement Validation of High Performance Board-to-Board 5-to-10 Gbps Interconnects

        Brian Vicich, Samtec
        Scott McMorrow, Teraspeed Consulting Group
        Tom Dagostino, Teraspeed Consulting Group
        James Bell, Teraspeed Consulting Group
        Bob Ross, Teraspeed Consulting Group
        Rob Hinz, Cider Designs


TF11        Interface Standards for Wireless Networking IC Implementation: Overview & Definition

        Patrick Yu, ULi Electronics
        Noman Rangwala, Analog Devices
        Agnes Yee, Hewlett Packard Company       
        Ken Buttle, Nimbus Wireless


TF13        Assertion-Based Verification With Psl: Paradigm Shift In Design Process

        Ben Cohen, VhdlCohen Training


TF14        Practical Multi GHz Clocks for ASIC and COT Designs

        Haris Basit, OEA International
        John Wood, MultiGig
        Ken Pedrotti, University of California Santa Cruz


TF15        Cray Supercomputer 3.2 Gb/s Serial Interconnect Simulation Using Full-wave Electromagnetics

        Lawrence I. Williams, Ansoft Corporation
        Steve Rousselle, Ansoft Corporation
        Bryan Boots, Ansoft Corporation


TF16        Reconfigurable Systems: Introduction to Adaptive Computing
        1 – Overview
        2 – ACM Development – Hardware and Software
        3 – Introduction to Dataflow Systems and SilverC
        4 – Control and Dataflow in an ACM
        5 – Scaling in an ACM

        Paul Master, QuickSilver Technology
发表于 2014-2-6 21:57:21 | 显示全部楼层
本帖最后由 chu 于 2014-2-6 22:08 编辑

非常好,感谢
发表于 2014-3-5 12:59:59 | 显示全部楼层
非常不错
发表于 2014-3-5 15:06:40 | 显示全部楼层
感謝樓主,下載來參考
发表于 2014-4-15 11:08:44 | 显示全部楼层
感謝分享~~
发表于 2014-6-22 11:10:59 | 显示全部楼层
电子设计业的最新资讯,感谢分享
发表于 2014-6-22 11:24:53 | 显示全部楼层
很好很强大,感谢
发表于 2014-8-17 03:06:45 | 显示全部楼层
很好很强大,感谢
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